A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

A Tcl-Library for scripted HDL generation

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

All Digital Phase-Locked Loop

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.

Basic JTAG / AXI demonstration on Xilinx's FPGA.

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

PDM Microphone peripheral written in SystemVerilog HDL

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

This project focuses on implementing a VGA interface and a screensaver for the Basys 3 FPGA Board. It involves generating VGA signals to display images stored in ROM, showcasing how to control and synchronize video output. The project culminates in programming the FPGA to display a functional screensaver on a VGA monitor.

Big Rofofo is a RISC-V RV32IMC_Zicsr processor with a 5-stage pipeline

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

A WIP RISC-V CPU implementation. Right now I'm working on implementing RV32I.

Little Rofofo is a RISC-V RV32IMC_Zicsr processor with a 5-stage pipeline