Veryl: A Modern Hardware Description Language
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May 5, 2025 - Rust
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systemverilog
Here are 20 public repositories matching this topic...
SystemVerilog parser library fully compliant with IEEE 1800-2017
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Mar 4, 2025 - Rust
A SystemVerilog Language Server
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Apr 5, 2025 - Rust
Package manager and build tool for VHDL/SystemVerilog
package-manager asic fpga cross-platform hardware vhdl rtl verilog build-tool command-line-tool systemverilog hdl agile-development
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May 1, 2025 - Rust
Determines the modules declared and instantiated in a SystemVerilog file
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Sep 23, 2024 - Rust
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
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Mar 3, 2025 - Rust
Hardware description language with Rust-like syntax
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Jan 17, 2025 - Rust
Example of using various technologies together in a Verilator simulation
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Jan 14, 2025 - Rust
Format Verilog/SystemVerilog code
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Sep 27, 2019 - Rust
Experimental cli to create HDL projects using Vivado, outside of their IDE.
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Oct 28, 2024 - Rust
Rust library to parse SystemVerilog / Verilog filelists, used in https://github.com/dalance/svlint
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May 16, 2022 - Rust
A simple SystemVerilog simulation tool written in rust
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Aug 25, 2024 - Rust
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Apr 1, 2025 - Rust
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