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Support sequence parallelism combined with pipeline parallelism #18243
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Signed-off-by: cascade812 <[email protected]>
👋 Hi! Thank you for contributing to the vLLM project. 💬 Join our developer Slack at https://slack.vllm.ai to discuss your PR in #pr-reviews, coordinate on features in #feat- channels, or join special interest groups in #sig- channels. Just a reminder: PRs would not trigger full CI run by default. Instead, it would only run Once the PR is approved and ready to go, your PR reviewer(s) can run CI to test the changes comprehensively before merging. To run CI, PR reviewers can either: Add 🚀 |
vllm/v1/worker/gpu_model_runner.py
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@@ -1172,6 +1184,7 @@ def execute_model( | |||
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if not get_pp_group().is_last_rank: | |||
# For mid-pipeline stages, return the hidden states. | |||
# print(f"cascade pp is not last rank, return hidden states") |
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for debug usage, will remove.
This pull request has merge conflicts that must be resolved before it can be |
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Great work! Left a few minor comments
Signed-off-by: cascade812 <[email protected]>
Signed-off-by: cascade812 <[email protected]>
…-project#18243) Signed-off-by: cascade812 <[email protected]> Signed-off-by: shaoyuyoung <[email protected]>
…-project#18243) Signed-off-by: cascade812 <[email protected]> Signed-off-by: Chenheli Hua <[email protected]>
this PR adds support for sp+pp scenario.