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Prepare portable packed vector types for RFCs #338

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Mar 5, 2018
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ccdc186
Prepare portable packed SIMD vector types for RFCs
gnzlbg Mar 2, 2018
804393d
enable backtrace and nocapture
gnzlbg Mar 2, 2018
8495a01
unalign load/store fail test by 1 byte
gnzlbg Mar 2, 2018
7e71717
update arm and aarch64 neon modules
gnzlbg Mar 2, 2018
4eb35b4
fix arm example
gnzlbg Mar 2, 2018
d97b2d7
fmt
gnzlbg Mar 2, 2018
ea3bc50
clippy and read example that rustfmt swallowed
gnzlbg Mar 2, 2018
ec79ac7
reductions should take self
gnzlbg Mar 2, 2018
695f05c
rename add/mul -> sum/product; delete other arith reductions
gnzlbg Mar 3, 2018
66a6af7
clean up fmt::LowerHex impl
gnzlbg Mar 3, 2018
f310e6b
revert incorret doc change
gnzlbg Mar 3, 2018
dd40e90
make Hash equivalent to [T; lanes()]
gnzlbg Mar 3, 2018
2586976
use travis_wait to increase timeout limit to 20 minutes
gnzlbg Mar 3, 2018
0d6418f
remove travis_wait; did not help
gnzlbg Mar 3, 2018
a49a061
implement reductions on top of the llvm.experimental.vector.reduction…
gnzlbg Mar 3, 2018
7520234
implement cmp for boolean vectors
gnzlbg Mar 3, 2018
06d6931
add missing eq impl file
gnzlbg Mar 3, 2018
e607abc
implement default
gnzlbg Mar 3, 2018
2559c57
rename llvm intrinsics
gnzlbg Mar 3, 2018
ab7d5b9
fix aarch64 example error
gnzlbg Mar 3, 2018
513e51a
replace #[inline(always)] with #[inline]
gnzlbg Mar 5, 2018
e773f6a
remove cargo clean from run.sh
gnzlbg Mar 5, 2018
b28011c
workaround broken product in aarch64
gnzlbg Mar 5, 2018
3f7594a
make boolean vector constructors const fn
gnzlbg Mar 5, 2018
57427dc
fix more reductions on aarch64
gnzlbg Mar 5, 2018
b2ee9ae
fix min/max reductions on aarch64
gnzlbg Mar 5, 2018
c19080e
remove whitespace
gnzlbg Mar 5, 2018
2be65ad
remove all boolean vector types except for b8xN
gnzlbg Mar 5, 2018
a74f06e
use a sum reduction fallback on aarch64
gnzlbg Mar 5, 2018
5169b8c
disable llvm add reduction for aarch64
gnzlbg Mar 5, 2018
84f4580
rename the llvm intrinsics to use llvm names
gnzlbg Mar 5, 2018
34e586a
remove old macros.rs file
gnzlbg Mar 5, 2018
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2 changes: 2 additions & 0 deletions ci/run.sh
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,8 @@ set -ex
# Tests are all super fast anyway, and they fault often enough on travis that
# having only one thread increases debuggability to be worth it.
export RUST_TEST_THREADS=1
export RUST_BACKTRACE=1
export RUST_TEST_NOCAPTURE=1

# FIXME(rust-lang-nursery/stdsimd#120) run-time feature detection for ARM Neon
case ${TARGET} in
Expand Down
2 changes: 1 addition & 1 deletion coresimd/aarch64/neon.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
#[cfg(test)]
use stdsimd_test::assert_instr;
use coresimd::simd_llvm::simd_add;
use coresimd::v128::f64x2;
use coresimd::simd::*;

/// Vector add.
#[inline]
Expand Down
28 changes: 14 additions & 14 deletions coresimd/arm/neon.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
use stdsimd_test::assert_instr;

use coresimd::simd_llvm::simd_add;
use coresimd::v64::*;
use coresimd::v128::*;
use coresimd::simd::*;
use convert::From;

/// Vector add.
#[inline]
Expand Down Expand Up @@ -140,8 +140,8 @@ pub unsafe fn vaddq_f32(a: f32x4, b: f32x4) -> f32x4 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
let a = a.as_i16x8();
let b = b.as_i16x8();
let a = i16x8::from(a);
let b = i16x8::from(b);
simd_add(a, b)
}

Expand All @@ -150,8 +150,8 @@ pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
let a = a.as_i32x4();
let b = b.as_i32x4();
let a = i32x4::from(a);
let b = i32x4::from(b);
simd_add(a, b)
}

Expand All @@ -160,8 +160,8 @@ pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
let a = a.as_i64x2();
let b = b.as_i64x2();
let a = i64x2::from(a);
let b = i64x2::from(b);
simd_add(a, b)
}

Expand All @@ -170,8 +170,8 @@ pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
let a = a.as_u16x8();
let b = b.as_u16x8();
let a = u16x8::from(a);
let b = u16x8::from(b);
simd_add(a, b)
}

Expand All @@ -180,8 +180,8 @@ pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
let a = a.as_u32x4();
let b = b.as_u32x4();
let a = u32x4::from(a);
let b = u32x4::from(b);
simd_add(a, b)
}

Expand All @@ -190,8 +190,8 @@ pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u32(a: u32x2, b: u32x2) -> u64x2 {
let a = a.as_u64x2();
let b = b.as_u64x2();
let a = u64x2::from(a);
let b = u64x2::from(b);
simd_add(a, b)
}

Expand Down
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