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Replace rustfmt::skip with alternate construction #299

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74 changes: 37 additions & 37 deletions drv/stm32h7-i2c/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -400,14 +400,14 @@ impl<'a> I2cController<'a> {
self.wait_until_notbusy()?;

if wlen > 0 {
#[rustfmt::skip]
i2c.cr2.modify(|_, w| { w
.nbytes().bits(wlen as u8)
.autoend().clear_bit()
.add10().clear_bit()
.sadd().bits((addr << 1).into())
.rd_wrn().clear_bit()
.start().set_bit()
i2c.cr2.modify(|_, w| {
w.nbytes().bits(wlen as u8);
w.autoend().clear_bit();
w.add10().clear_bit();
w.sadd().bits((addr << 1).into());
w.rd_wrn().clear_bit();
w.start().set_bit();
w
});

let mut pos = 0;
Expand Down Expand Up @@ -487,25 +487,25 @@ impl<'a> I2cController<'a> {
// read).
//
if let ReadLength::Fixed(rlen) = rlen {
#[rustfmt::skip]
i2c.cr2.modify(|_, w| { w
.nbytes().bits(rlen as u8)
.autoend().clear_bit()
.add10().clear_bit()
.sadd().bits((addr << 1).into())
.rd_wrn().set_bit()
.start().set_bit()
i2c.cr2.modify(|_, w| {
w.nbytes().bits(rlen as u8);
w.autoend().clear_bit();
w.add10().clear_bit();
w.sadd().bits((addr << 1).into());
w.rd_wrn().set_bit();
w.start().set_bit();
w
});
} else {
#[rustfmt::skip]
i2c.cr2.modify(|_, w| { w
.nbytes().bits(1)
.autoend().clear_bit()
.reload().set_bit()
.add10().clear_bit()
.sadd().bits((addr << 1).into())
.rd_wrn().set_bit()
.start().set_bit()
i2c.cr2.modify(|_, w| {
w.nbytes().bits(1);
w.autoend().clear_bit();
w.reload().set_bit();
w.add10().clear_bit();
w.sadd().bits((addr << 1).into());
w.rd_wrn().set_bit();
w.start().set_bit();
w
});
}

Expand Down Expand Up @@ -549,10 +549,10 @@ impl<'a> I2cController<'a> {
let byte: u8 = i2c.rxdr.read().rxdata().bits();

if rlen == ReadLength::Variable {
#[rustfmt::skip]
i2c.cr2.modify(|_, w| { w
.nbytes().bits(byte)
.reload().clear_bit()
i2c.cr2.modify(|_, w| {
w.nbytes().bits(byte);
w.reload().clear_bit();
w
});

rlen = ReadLength::Fixed(byte.into());
Expand Down Expand Up @@ -628,14 +628,14 @@ impl<'a> I2cController<'a> {

ringbuf_entry!(Trace::Konami(*op));

#[rustfmt::skip]
i2c.cr2.modify(|_, w| { w
.nbytes().bits(0u8)
.autoend().clear_bit()
.add10().clear_bit()
.sadd().bits((addr << 1).into())
.rd_wrn().bit(opval)
.start().set_bit()
i2c.cr2.modify(|_, w| {
w.nbytes().bits(0u8);
w.autoend().clear_bit();
w.add10().clear_bit();
w.sadd().bits((addr << 1).into());
w.rd_wrn().bit(opval);
w.start().set_bit();
w
});

// All done; now block until our transfer is complete -- or until
Expand Down
106 changes: 51 additions & 55 deletions drv/stm32h7-qspi/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -63,27 +63,25 @@ impl Qspi {
assert!(divider > 0);
assert!(l2size > 0 && l2size < 64);

#[rustfmt::skip]
self.reg.cr.write(|w| unsafe {
// Divide kernel clock by the divider, which means setting
// prescaler to one less.
w.prescaler().bits(divider - 1);
// In both read and write modes we try to get 16 bytes into the
// FIFO before bothering to wake up.
w.fthres().bits(FIFO_THRESH as u8 - 1);
// On.
w.en().set_bit();
w
// Divide kernel clock by the divider, which means setting
// prescaler to one less.
.prescaler().bits(divider - 1)
// In both read and write modes we try to get 16 bytes into the
// FIFO before bothering to wake up.
.fthres().bits(FIFO_THRESH as u8 - 1)
// On.
.en().set_bit()
});
#[rustfmt::skip]
self.reg.dcr.write(|w| unsafe {
// Flash size is recorded as log2 minus 1.
w.fsize().bits(l2size - 1);
// CS high time: 1 cycle between (arbitrary)
w.csht().bits(1);
// Clock mode 0.
w.ckmode().clear_bit();
w
// Flash size is recorded as log2 minus 1.
.fsize().bits(l2size - 1)
// CS high time: 1 cycle between (arbitrary)
.csht().bits(1)
// Clock mode 0.
.ckmode().clear_bit()
});
}

Expand Down Expand Up @@ -158,25 +156,24 @@ impl Qspi {

// Note: if we aren't using an address, this write will kick things off.
// Otherwise it's the AR write below.
#[rustfmt::skip]
self.reg.ccr.write(|w| unsafe {
// Indirect write
w.fmode().bits(0b00);
// Data on single line, or no data
w.dmode().bits(if data.is_empty() { 0b00 } else { 0b01 });
// Dummy cycles = 0 for this
w.dcyc().bits(0);
// No alternate bytes
w.abmode().bits(0);
// 32-bit address, if present.
w.adsize().bits(if addr.is_some() { 0b11 } else { 0b00 });
// ...on one line for now, if present.
w.admode().bits(if addr.is_some() { 0b01 } else { 0b00 });
// Instruction on single line
w.imode().bits(0b01);
// And, the op
w.instruction().bits(command as u8);
w
// Indirect write
.fmode().bits(0b00)
// Data on single line, or no data
.dmode().bits(if data.is_empty() { 0b00 } else { 0b01 })
// Dummy cycles = 0 for this
.dcyc().bits(0)
// No alternate bytes
.abmode().bits(0)
// 32-bit address, if present.
.adsize().bits(if addr.is_some() { 0b11 } else { 0b00 })
// ...on one line for now, if present.
.admode().bits(if addr.is_some() { 0b01 } else { 0b00 })
// Instruction on single line
.imode().bits(0b01)
// And, the op
.instruction().bits(command as u8)
});
if let Some(addr) = addr {
self.reg.ar.write(|w| unsafe { w.address().bits(addr) });
Expand Down Expand Up @@ -250,25 +247,24 @@ impl Qspi {
// hanging around from some previous transfer -- ensure this:
self.reg.fcr.write(|w| w.ctcf().set_bit());

#[rustfmt::skip]
self.reg.ccr.write(|w| unsafe {
// Indirect read
w.fmode().bits(0b01);
// Data on single line, or no data
w.dmode().bits(if out.is_empty() { 0b00 } else { 0b01 });
// Dummy cycles = 0 for this
w.dcyc().bits(0);
// No alternate bytes
w.abmode().bits(0);
// 32-bit address if present.
w.adsize().bits(if addr.is_some() { 0b11 } else { 0b00 });
// ...on one line for now, if present.
w.admode().bits(if addr.is_some() { 0b01 } else { 0b00 });
// Instruction on single line
w.imode().bits(0b01);
// And, the op
w.instruction().bits(command as u8);
w
// Indirect read
.fmode().bits(0b01)
// Data on single line, or no data
.dmode().bits(if out.is_empty() { 0b00 } else { 0b01 })
// Dummy cycles = 0 for this
.dcyc().bits(0)
// No alternate bytes
.abmode().bits(0)
// 32-bit address if present.
.adsize().bits(if addr.is_some() { 0b11 } else { 0b00 })
// ...on one line for now, if present.
.admode().bits(if addr.is_some() { 0b01 } else { 0b00 })
// Instruction on single line
.imode().bits(0b01)
// And, the op
.instruction().bits(command as u8)
});
if let Some(addr) = addr {
self.reg.ar.write(|w| unsafe { w.address().bits(addr) });
Expand All @@ -289,11 +285,11 @@ impl Qspi {
self.reg.cr.modify(|_, w| w.ftie().set_bit());
} else {
// We want the transfer-complete event
#[rustfmt::skip]
self.reg.cr.modify(|_, w|
w.ftie().clear_bit()
.tcie().set_bit()
);
self.reg.cr.modify(|_, w| {
w.ftie().clear_bit();
w.tcie().set_bit();
w
});
}

// Unmask our interrupt.
Expand Down
31 changes: 15 additions & 16 deletions drv/stm32h7-spi/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -80,24 +80,23 @@ impl Spi {
// TODO: C driver has some bits about twiddling SSI state to avoid MODF.
// I've hardcoded what I believe is the equivalent result here.

#[rustfmt::skip]
self.reg.cfg2.write(|w| {
// This bit determines if software manages SS (SSM = 1) or
// hardware (SSM = 0). Let hardware set SS appropriately.
w.ssm().clear_bit();
// SS output enabled; but not necessarily routed to a pin
// (caller determines that)
w.ssoe().enabled();
// Don't glitch pins when being reconfigured.
w.afcntr().controlled();
// This is currently a host-only driver.
w.master().set_bit();
w.comm().variant(comm);
w.lsbfrst().variant(lsbfrst);
w.cpha().variant(cpha);
w.cpol().variant(cpol);
w.ssom().variant(ssom);
w
// This bit determines if software manages SS (SSM = 1) or
// hardware (SSM = 0). Let hardware set SS appropriately.
.ssm().clear_bit()
// SS output enabled; but not necessarily routed to a pin
// (caller determines that)
.ssoe().enabled()
// Don't glitch pins when being reconfigured.
.afcntr().controlled()
// This is currently a host-only driver.
.master().set_bit()
.comm().variant(comm)
.lsbfrst().variant(lsbfrst)
.cpha().variant(cpha)
.cpol().variant(cpol)
.ssom().variant(ssom)
});

self.reg.cr1.write(|w| w.ssi().set_bit());
Expand Down