[AMDGPU] Remove FeatureForceStoreSC0SC1

[ritter-x2a]

This was only used for gfx940 and gfx941, which have since been removed.

For SWDEV-512631

[ritter-x2a]

• [AMDGPU][docs][NFC] Replace gfx940 with gfx942 in the gfx940 ISA doc #126906
• [AMDGPU][docs] Replace gfx940 and gfx941 with gfx942 in llvm/docs #126887
• [AMDGPU] Remove FeatureForceStoreSC0SC1 #126878 👈 (View in Graphite)
• [AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm #126763
• [AMDGPU][clang] Replace gfx940 and gfx941 with gfx942 in clang #126762
• [AMDGPU][MLIR] Replace gfx940 and gfx941 with gfx942 in MLIR #125836
• [AMDGPU] Add missing gfx architectures to AddFlangOffloadRuntime.cmake #125827
• [AMDGPU] Replace gfx940 and gfx941 with gfx942 in offload and libclc #125826
• [AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test #125711
• main

This stack of pull requests is managed by Graphite. Learn more about stacking.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Fabian Ritter (ritter-x2a)

Changes

This was only used for gfx940 and gfx941, which have since been removed.

For SWDEV-512631

---

Full diff: https://github.com/llvm/llvm-project/pull/126878.diff

3 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (-6)
• (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (-3)
• (modified) llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp (-20)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 3aabca49b249e..effc8d2ed6b49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1040,12 +1040,6 @@ def FeatureVALUTransUseHazard : SubtargetFeature<"valu-trans-use-hazard",
   "Hazard when TRANS instructions are closely followed by a use of the result"
 >;
 
-def FeatureForceStoreSC0SC1 : SubtargetFeature<"force-store-sc0-sc1",
-  "HasForceStoreSC0SC1",
-  "true",
-  "Has SC0 and SC1 on stores"
->;
-
 def FeatureSALUFloatInsts : SubtargetFeature<"salu-float",
   "HasSALUFloatInsts",
   "true",
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index f7c5c472c93a5..6664a70572ded 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -246,7 +246,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   bool HasMADIntraFwdBug = false;
   bool HasVOPDInsts = false;
   bool HasVALUTransUseHazard = false;
-  bool HasForceStoreSC0SC1 = false;
   bool HasRequiredExportPriority = false;
   bool HasVmemWriteVgprInOrder = false;
   bool HasAshrPkInsts = false;
@@ -1264,8 +1263,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
 
   bool hasCvtScaleForwardingHazard() const { return GFX950Insts; }
 
-  bool hasForceStoreSC0SC1() const { return HasForceStoreSC0SC1; }
-
   bool requiresCodeObjectV6() const { return RequiresCOV6; }
 
   bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 79fb36acc0ea7..34953f9c08db7 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -359,11 +359,6 @@ class SICacheControl {
 
   /// Virtual destructor to allow derivations to be deleted.
   virtual ~SICacheControl() = default;
-
-  virtual bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
-                                   MachineBasicBlock::iterator &MI) const {
-    return false;
-  }
 };
 
 class SIGfx6CacheControl : public SICacheControl {
@@ -517,20 +512,6 @@ class SIGfx940CacheControl : public SIGfx90ACacheControl {
   bool insertRelease(MachineBasicBlock::iterator &MI, SIAtomicScope Scope,
                      SIAtomicAddrSpace AddrSpace, bool IsCrossAddrSpaceOrdering,
                      Position Pos) const override;
-
-  bool tryForceStoreSC0SC1(const SIMemOpInfo &MOI,
-                           MachineBasicBlock::iterator &MI) const override {
-    bool Changed = false;
-    if (ST.hasForceStoreSC0SC1() &&
-        (MOI.getInstrAddrSpace() & (SIAtomicAddrSpace::SCRATCH |
-                                    SIAtomicAddrSpace::GLOBAL |
-                                    SIAtomicAddrSpace::OTHER)) !=
-         SIAtomicAddrSpace::NONE) {
-      Changed |= enableSC0Bit(MI);
-      Changed |= enableSC1Bit(MI);
-    }
-    return Changed;
-  }
 };
 
 class SIGfx10CacheControl : public SIGfx7CacheControl {
@@ -2820,7 +2801,6 @@ bool SIMemoryLegalizer::runOnMachineFunction(MachineFunction &MF) {
         Changed |= expandLoad(*MOI, MI);
       else if (const auto &MOI = MOA.getStoreInfo(MI)) {
         Changed |= expandStore(*MOI, MI);
-        Changed |= CC->tryForceStoreSC0SC1(*MOI, MI);
       } else if (const auto &MOI = MOA.getAtomicFenceInfo(MI))
         Changed |= expandAtomicFence(*MOI, MI);
       else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI))

[ritter-x2a]

Merge activity

• Feb 19, 3:48 AM EST: A user started a stack merge that includes this pull request via Graphite.
• Feb 19, 4:24 AM EST: Graphite rebased this pull request as part of a merge.
• Feb 19, 4:26 AM EST: A user merged this pull request with Graphite.