Upstream updates

[astro]

There have been breaking changes in svd2rust and the cortex-m crate. I re-ran svd2rust. Unfortunately, this drops all of the manual improvements.

[astro]

Here's more on the motivation behind the new I/O model: http://blog.japaric.io/brave-new-io/

[dkarwowski]

Ill likely take a look at this tomorrow or sometime during the weekend, and regenerate with the customized patch.

If you want, the patched svd is checked in under the dev branch and you can try regenerating with that, too.

[astro]

Sorry, but svd2rust is missing SPI1 with the changes:

stm32f429x $ svd2rust --target cortex-m -i STM32F429x.svd
error: No register SPI1 in peripheral SPI1
note: run with `RUST_BACKTRACE=1` for a backtrace

BTW:

diff --git STM32F429x.svd STM32F429x.svd
index 7550930..95e9702 100644
--- STM32F429x.svd
+++ STM32F429x.svd
@@ -13297,7 +13297,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
                   <description>Next transfer is CRC</description>
                   <value>1</value>
                 </enumeratedValue>
-              </enumeratedValue>
+              </enumeratedValues>
             </field>
             <field>
               <name>DFF</name>
@@ -13323,7 +13323,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitOffset>10</bitOffset>
               <bitWidth>1</bitWidth>
               <enumeratedValues derivedFrom="SPI1.CR1.BIDIOE.ENABLER">
-              </enumeratedvalues>
+              </enumeratedValues>
             </field>
             <field>
               <name>SSM</name>

[astro]

No pressure, just a reminder. :-) Thanks in advance!

[astro]

Nevermind, I have switched to crate stm32f429 which has appeared in the meanwhile. :-)