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fix: missing constants and AtomicU64 for --all-features on riscv32 target #11

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31 changes: 31 additions & 0 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
name: Build & Check CI

on: [push, pull_request]

jobs:
ci:
runs-on: ubuntu-latest
strategy:
fail-fast: false
matrix:
rust-toolchain: [nightly, nightly-2024-12-04]
targets: [x86_64-unknown-linux-gnu, x86_64-unknown-none, riscv64gc-unknown-none-elf, riscv32imafc-unknown-none-elf, aarch64-unknown-none-softfloat]
features: ["", "--all-features"]
steps:
- uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@nightly
with:
toolchain: ${{ matrix.rust-toolchain }}
components: rust-src, clippy, rustfmt
targets: ${{ matrix.targets }}
- name: Check rust version
run: rustc --version --verbose
- name: Check code format
run: cargo fmt --all -- --check
- name: Clippy
run: cargo clippy --target ${{ matrix.targets }} ${{ matrix.features }}
- name: Build
run: cargo build --target ${{ matrix.targets }} ${{ matrix.features }}
- name: Unit test
if: ${{ matrix.targets == 'x86_64-unknown-linux-gnu' }}
run: cargo test --target ${{ matrix.targets }} ${{ matrix.features }} -- --nocapture
97 changes: 51 additions & 46 deletions src/arch/riscv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -61,36 +61,40 @@ impl TaskContext {
}

#[cfg(target_arch = "riscv32")]
core::arch::global_asm!(
r"
macro_rules! STR_LDR {
() => {
r"
.ifndef XLENB
.equ XLENB, 4

.macro LDR rd, rs, off
lw \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sw \rs2, \off*XLENB(\rs1)
.endm
.macro LDR rd, rs, off
lw \rd, \off*XLENB(\rs)
.endm

.endif"
);
};
}

#[cfg(target_arch = "riscv64")]
core::arch::global_asm!(
r"
macro_rules! STR_LDR {
() => {
r"
.ifndef XLENB
.equ XLENB, 8

.macro LDR rd, rs, off
ld \rd, \off*XLENB(\rs)
.endm
.macro STR rs2, rs1, off
sd \rs2, \off*XLENB(\rs1)
.endm
.macro LDR rd, rs, off
ld \rd, \off*XLENB(\rs)
.endm

.endif",
);
.endif"
};
}

#[naked]
/// Switches the context from the current task to the next task.
Expand All @@ -101,40 +105,41 @@ core::arch::global_asm!(
pub unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task: &TaskContext) {
unsafe {
naked_asm!(
STR_LDR!(),
"
// save old context (callee-saved registers)
STR ra, a0, 0
STR sp, a0, 1
STR s0, a0, 2
STR s1, a0, 3
STR s2, a0, 4
STR s3, a0, 5
STR s4, a0, 6
STR s5, a0, 7
STR s6, a0, 8
STR s7, a0, 9
STR s8, a0, 10
STR s9, a0, 11
STR s10, a0, 12
STR s11, a0, 13

// restore new context
LDR s11, a1, 13
LDR s10, a1, 12
LDR s9, a1, 11
LDR s8, a1, 10
LDR s7, a1, 9
LDR s6, a1, 8
LDR s5, a1, 7
LDR s4, a1, 6
LDR s3, a1, 5
LDR s2, a1, 4
LDR s1, a1, 3
LDR s0, a1, 2
LDR sp, a1, 1
LDR ra, a1, 0

ret",
// save old context (callee-saved registers)
STR ra, a0, 0
STR sp, a0, 1
STR s0, a0, 2
STR s1, a0, 3
STR s2, a0, 4
STR s3, a0, 5
STR s4, a0, 6
STR s5, a0, 7
STR s6, a0, 8
STR s7, a0, 9
STR s8, a0, 10
STR s9, a0, 11
STR s10, a0, 12
STR s11, a0, 13

// restore new context
LDR s11, a1, 13
LDR s10, a1, 12
LDR s9, a1, 11
LDR s8, a1, 10
LDR s7, a1, 9
LDR s6, a1, 8
LDR s5, a1, 7
LDR s4, a1, 6
LDR s3, a1, 5
LDR s2, a1, 4
LDR s1, a1, 3
LDR s0, a1, 2
LDR sp, a1, 1
LDR ra, a1, 0

ret",
)
}
}
46 changes: 22 additions & 24 deletions src/task.rs
Original file line number Diff line number Diff line change
@@ -1,24 +1,22 @@
#[cfg(feature = "tls")]
use crate::tls::TlsArea;

use crate::{TaskStack, TimeStat, arch::TaskContext};
extern crate alloc;
use crate::{TaskStack, TimeStat, arch::TaskContext};
use alloc::{boxed::Box, string::String};

#[allow(unused_imports)]
use core::{
cell::UnsafeCell,
fmt,
sync::atomic::{AtomicBool, AtomicI32, AtomicU8, AtomicU64, AtomicUsize, Ordering},
sync::atomic::{AtomicBool, AtomicI32, AtomicUsize, Ordering},
};
use memory_addr::{VirtAddr, align_up_4k};

/// A unique identifier for a thread.
#[derive(Debug, Clone, Copy, Eq, PartialEq)]
pub struct TaskId(u64);
pub struct TaskId(usize);
pub const MAX_RT_PRIO: usize = 99;

static ID_COUNTER: AtomicU64 = AtomicU64::new(1);
static ID_COUNTER: AtomicUsize = AtomicUsize::new(1);
impl TaskId {
/// Create a new task ID.
pub fn new() -> Self {
Expand All @@ -27,7 +25,7 @@ impl TaskId {

/// Convert the task ID to a `u64`.
pub const fn as_u64(&self) -> u64 {
self.0
self.0 as u64
}

#[cfg(feature = "monolithic")]
Expand Down Expand Up @@ -152,7 +150,7 @@ pub struct TaskInner {
ctx: UnsafeCell<TaskContext>,

#[cfg(feature = "monolithic")]
process_id: AtomicU64,
process_id: AtomicUsize,

#[cfg(feature = "monolithic")]
/// 是否是所属进程下的主线程
Expand All @@ -166,20 +164,20 @@ pub struct TaskInner {
pub page_table_token: UnsafeCell<usize>,

#[cfg(feature = "monolithic")]
set_child_tid: AtomicU64,
set_child_tid: AtomicUsize,

#[cfg(feature = "monolithic")]
clear_child_tid: AtomicU64,
clear_child_tid: AtomicUsize,

/// 时间统计, 无论是否为宏内核架构都可能被使用到
#[allow(unused)]
time: UnsafeCell<TimeStat>,

#[cfg(feature = "monolithic")]
/// TODO: to support the sched_setaffinity
///
/// TODO: move to the upper layer
pub cpu_set: AtomicU64,
#[cfg(feature = "monolithic")]
pub cpu_set: AtomicUsize,

#[cfg(feature = "monolithic")]
/// The scheduler status of the task, which defines the scheduling policy and priority
Expand Down Expand Up @@ -258,7 +256,7 @@ impl TaskInner {

t.entry = Some(Box::into_raw(Box::new(entry)));

t.process_id.store(process_id, Ordering::Release);
t.process_id.store(process_id as _, Ordering::Release);

t.page_table_token = UnsafeCell::new(page_table_token);

Expand Down Expand Up @@ -398,17 +396,17 @@ impl TaskInner {
impl TaskInner {
/// store the child thread ID at the location pointed to by child_tid in clone args
pub fn set_child_tid(&self, tid: usize) {
self.set_child_tid.store(tid as u64, Ordering::Release)
self.set_child_tid.store(tid, Ordering::Release)
}

/// clear (zero) the child thread ID at the location pointed to by child_tid in clone args
pub fn set_clear_child_tid(&self, tid: usize) {
self.clear_child_tid.store(tid as u64, Ordering::Release)
self.clear_child_tid.store(tid, Ordering::Release)
}

/// get the pointer to the child thread ID
pub fn get_clear_child_tid(&self) -> usize {
self.clear_child_tid.load(Ordering::Acquire) as usize
self.clear_child_tid.load(Ordering::Acquire)
}

#[inline]
Expand All @@ -428,13 +426,13 @@ impl TaskInner {
#[inline]
/// get the process ID of the task
pub fn get_process_id(&self) -> u64 {
self.process_id.load(Ordering::Acquire)
self.process_id.load(Ordering::Acquire) as _
}

#[inline]
/// set the process ID of the task
pub fn set_process_id(&self, process_id: u64) {
self.process_id.store(process_id, Ordering::Release);
self.process_id.store(process_id as _, Ordering::Release);
}

// /// 获取内核栈的第一个trap上下文
Expand Down Expand Up @@ -464,12 +462,12 @@ impl TaskInner {
set_size * 4
};
let now_mask = mask & 1 << ((len) - 1);
self.cpu_set.store(now_mask as u64, Ordering::Release)
self.cpu_set.store(now_mask as _, Ordering::Release)
}

/// to get the CPU set
pub fn get_cpu_set(&self) -> usize {
self.cpu_set.load(Ordering::Acquire) as usize
self.cpu_set.load(Ordering::Acquire)
}

/// set the scheduling policy and priority
Expand Down Expand Up @@ -533,7 +531,7 @@ impl TaskInner {
time: UnsafeCell::new(TimeStat::new()),

#[cfg(feature = "monolithic")]
process_id: AtomicU64::new(0),
process_id: AtomicUsize::new(0),

#[cfg(feature = "monolithic")]
is_leader: AtomicBool::new(false),
Expand All @@ -542,14 +540,14 @@ impl TaskInner {
page_table_token: UnsafeCell::new(0),

#[cfg(feature = "monolithic")]
set_child_tid: AtomicU64::new(0),
set_child_tid: AtomicUsize::new(0),

#[cfg(feature = "monolithic")]
clear_child_tid: AtomicU64::new(0),
clear_child_tid: AtomicUsize::new(0),

#[cfg(feature = "monolithic")]
// 一开始默认都可以运行在每个CPU上
cpu_set: AtomicU64::new(0),
cpu_set: AtomicUsize::new(0),

#[cfg(feature = "monolithic")]
sched_status: UnsafeCell::new(SchedStatus {
Expand Down
2 changes: 1 addition & 1 deletion src/tls.rs
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ cfg_if::cfg_if! {
} else if #[cfg(target_arch = "aarch64")] {
const TCB_SIZE: usize = 0;
const GAP_ABOVE_TP: usize = 16;
} else if #[cfg(target_arch = "riscv64")] {
} else if #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))] {
const TCB_SIZE: usize = 0;
const GAP_ABOVE_TP: usize = 0;
}
Expand Down