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Merge pull request #82 from fpistm/Disco_F746_ethernet
Enabling Ethernet for Discovery F746
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/**
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******************************************************************************
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* @file LwIP/LwIP_HTTP_Server_Raw/Inc/lwipopts.h
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* @author MCD Application Team
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* @version V1.5.0
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* @date 17-February-2017
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* @brief lwIP Options Configuration.
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics International N.V.
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* All rights reserved.</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted, provided that the following conditions are met:
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*
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* 1. Redistribution of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of other
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* contributors to this software may be used to endorse or promote products
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* derived from this software without specific written permission.
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* 4. This software, including modifications and/or derivative works of this
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* software, must execute solely and exclusively on microcontroller or
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* microprocessor devices manufactured by or for STMicroelectronics.
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* 5. Redistribution and use of this software other than as permitted under
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* this license is void and will automatically terminate your rights under
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* this license.
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*
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* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
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* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
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* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __LWIPOPTS_H__
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#define __LWIPOPTS_H__
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/**
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* NO_SYS==1: Provides VERY minimal functionality. Otherwise,
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* use lwIP facilities.
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*/
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#define NO_SYS 1
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/**
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* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
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* critical regions during buffer allocation, deallocation and memory
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* allocation and deallocation.
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*/
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#define SYS_LIGHTWEIGHT_PROT 0
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/* ---------- Memory options ---------- */
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/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
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lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
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byte alignment -> define MEM_ALIGNMENT to 2. */
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#define MEM_ALIGNMENT 4
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/* MEM_SIZE: the size of the heap memory. If the application will send
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a lot of data that needs to be copied, this should be set high. */
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#define MEM_SIZE (10*1024)
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/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
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sends a lot of data out of ROM (or other static memory), this
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should be set high. */
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#define MEMP_NUM_PBUF 10
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/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
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per active UDP "connection". */
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#define MEMP_NUM_UDP_PCB 6
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/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
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connections. */
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#define MEMP_NUM_TCP_PCB 10
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/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
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connections. */
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#define MEMP_NUM_TCP_PCB_LISTEN 6
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/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
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segments. */
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#define MEMP_NUM_TCP_SEG 8
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/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
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timeouts. */
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#define MEMP_NUM_SYS_TIMEOUT 10
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/* ---------- Pbuf options ---------- */
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/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
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#define PBUF_POOL_SIZE 8
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/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
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#define PBUF_POOL_BUFSIZE 1524
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/* ---------- TCP options ---------- */
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#define LWIP_TCP 1
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#define TCP_TTL 255
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/* Controls if TCP should queue segments that arrive out of
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order. Define to 0 if your device is low on memory. */
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#define TCP_QUEUE_OOSEQ 0
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/* TCP Maximum segment size. */
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#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */
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/* TCP sender buffer space (bytes). */
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#define TCP_SND_BUF (4*TCP_MSS)
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/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
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as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */
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#define TCP_SND_QUEUELEN (2* TCP_SND_BUF/TCP_MSS)
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/* TCP receive window. */
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#define TCP_WND (2*TCP_MSS)
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/* ---------- ICMP options ---------- */
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#define LWIP_ICMP 1
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/* ---------- DHCP options ---------- */
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#define LWIP_DHCP 1
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/* ---------- DNS options ---------- */
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#define LWIP_DNS 1
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/* ---------- UDP options ---------- */
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#define LWIP_UDP 1
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#define UDP_TTL 255
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/* ---------- Statistics options ---------- */
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#define LWIP_STATS 0
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/* ---------- link callback options ---------- */
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/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
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* whenever the link changes (i.e., link down)
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*/
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#define LWIP_NETIF_LINK_CALLBACK 1
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/*
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--------------------------------------
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---------- Checksum options ----------
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--------------------------------------
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*/
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/*
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The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
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- To use this feature let the following define uncommented.
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- To disable it and process by CPU comment the the checksum.
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*/
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#define CHECKSUM_BY_HARDWARE
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#ifdef CHECKSUM_BY_HARDWARE
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/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
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#define CHECKSUM_GEN_IP 0
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/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
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#define CHECKSUM_GEN_UDP 0
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/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
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#define CHECKSUM_GEN_TCP 0
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/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
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#define CHECKSUM_CHECK_IP 0
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/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
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#define CHECKSUM_CHECK_UDP 0
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/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
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#define CHECKSUM_CHECK_TCP 0
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/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/
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#define CHECKSUM_GEN_ICMP 0
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#else
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/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
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#define CHECKSUM_GEN_IP 1
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/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
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#define CHECKSUM_GEN_UDP 1
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/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
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#define CHECKSUM_GEN_TCP 1
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/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
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#define CHECKSUM_CHECK_IP 1
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/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
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#define CHECKSUM_CHECK_UDP 1
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/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
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#define CHECKSUM_CHECK_TCP 1
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/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/
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#define CHECKSUM_GEN_ICMP 1
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#endif
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/*
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----------------------------------------------
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---------- Sequential layer options ----------
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----------------------------------------------
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*/
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/**
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* LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
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*/
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#define LWIP_NETCONN 0
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/*
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------------------------------------
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---------- Socket options ----------
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------------------------------------
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*/
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/**
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* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
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*/
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#define LWIP_SOCKET 0
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/*
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------------------------------------
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---------- httpd options ----------
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------------------------------------
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*/
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/** Set this to 1 to support CGI */
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#define LWIP_HTTPD_CGI 1
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/** Set this to 1 to support SSI (Server-Side-Includes) */
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#define LWIP_HTTPD_SSI 1
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/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the
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* file system (to prevent changing the file included in CVS) */
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#define HTTPD_USE_CUSTOM_FSDATA 1
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/*
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------------------------------------
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---------- Custom options ----------
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------------------------------------
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*/
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/** Enables the Ethernet peripheral in RMII mode. If not defined, MII mode will
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be enabled. Pin mapping must be configured for the selected mode
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(see PinMap_Ethernet in PeripheralPins.c). */
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#define ETHERNET_RMII_MODE_CONFIGURATION 1
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/** Uncomment this line to use the ethernet input in interrupt mode.
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* NOTE: LwIP stack documentation recommends to use the polling mode without
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* an operating system. */
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//#define ETH_INPUT_USE_IT 1
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#endif /* __LWIPOPTS_H__ */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

variants/DISCO_F746NG/PeripheralPins.c

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -384,3 +384,41 @@ const PinMap PinMap_CAN_TD[] = {
384384
// {PH13, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
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{NC, NP, 0}
386386
};
387+
388+
//*** ETHERNET ***
389+
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/* Configured for RMII mapping */
391+
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#ifdef HAL_ETH_MODULE_ENABLED
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const PinMap PinMap_Ethernet[] = {
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// {PA0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
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{PA1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK|ETH_RX_CLK
396+
{PA2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO
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// {PA3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL
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{PA7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV|ETH_RX_DV
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// {PB0, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
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// {PB1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
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// {PB5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
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// {PB8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
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// {PB10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
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// {PB11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
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// {PB12, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
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// {PB13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
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{PC1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC
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// {PC2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2
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// {PC3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK
410+
{PC4, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0
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{PC5, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1
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// {PE2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
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// {PG8, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
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{PG11, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
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{PG13, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
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{PG14, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
417+
// {PH2, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
418+
// {PH3, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL
419+
// {PH6, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
420+
// {PH7, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
421+
// {PI10, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
422+
{NC, NP, 0}
423+
};
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#endif

variants/DISCO_F746NG/stm32f7xx_hal_conf.h

Lines changed: 19 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@
6262
// #define HAL_DCMI_MODULE_ENABLED
6363
#define HAL_DMA_MODULE_ENABLED
6464
// #define HAL_DMA2D_MODULE_ENABLED
65-
// #define HAL_ETH_MODULE_ENABLED
65+
#define HAL_ETH_MODULE_ENABLED
6666
#define HAL_FLASH_MODULE_ENABLED
6767
// #define HAL_NAND_MODULE_ENABLED
6868
// #define HAL_NOR_MODULE_ENABLED
@@ -184,18 +184,17 @@
184184
#define MAC_ADDR4 0U
185185
#define MAC_ADDR5 0U
186186

187-
/* Definition of the Ethernet driver buffers size and count */
187+
/* Definition of the Ethernet driver buffers size and count */
188188
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
189189
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
190-
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
191-
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
190+
#define ETH_RXBUFNB (4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
191+
#define ETH_TXBUFNB (4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
192192

193193
/* Section 2: PHY configuration section */
194-
195-
/* DP83848 PHY Address*/
196-
#define DP83848_PHY_ADDRESS 0x01U
197-
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
198-
#define PHY_RESET_DELAY 0x000000FFU
194+
/* LAN8742A PHY Address*/
195+
#define LAN8742A_PHY_ADDRESS 0x00U
196+
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
197+
#define PHY_RESET_DELAY 0x00000FFFU
199198
/* PHY Configuration delay */
200199
#define PHY_CONFIG_DELAY 0x00000FFFU
201200

@@ -204,9 +203,9 @@
204203

205204
/* Section 3: Common PHY Registers */
206205

207-
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
208-
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
209-
206+
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
207+
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
208+
210209
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
211210
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
212211
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
@@ -221,22 +220,18 @@
221220
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
222221
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
223222
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
224-
223+
225224
/* Section 4: Extended PHY Registers */
226225

227-
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
228-
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */
229-
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
230-
231-
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
232-
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
233-
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
226+
#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */
227+
228+
#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */
229+
#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */
234230

235-
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
236-
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
237231

238-
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
239-
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
232+
#define PHY_ISFR ((uint16_t)0x01DU) /*!< PHY Interrupt Source Flag register Offset */
233+
#define PHY_IMR ((uint16_t)0x001E) /*!< PHY Interrupt Mask register Offset */
234+
#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */
240235

241236
/* ################## SPI peripheral configuration ########################## */
242237

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