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geosmallfpistm
andauthored
variant: add F722R(C-E)T/F730R8T/F732RET
Signed-off-by: George Small <[email protected]> Co-authored-by: Frederic Pillon <[email protected]>
1 parent 4be5ca1 commit e2f8bc3

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+268
-2
lines changed

3 files changed

+268
-2
lines changed

boards.txt

+32
Original file line numberDiff line numberDiff line change
@@ -2906,6 +2906,38 @@ GenF7.build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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GenF7.build.series=STM32F7xx
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GenF7.build.cmsis_lib_gcc=arm_cortexM7lfsp_math
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2909+
# Generic F722RCTx
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GenF7.menu.pnum.GENERIC_F722RCTX=Generic F722RCTx
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GenF7.menu.pnum.GENERIC_F722RCTX.upload.maximum_size=262144
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GenF7.menu.pnum.GENERIC_F722RCTX.upload.maximum_data_size=196608
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GenF7.menu.pnum.GENERIC_F722RCTX.build.board=GENERIC_F722RCTX
2914+
GenF7.menu.pnum.GENERIC_F722RCTX.build.product_line=STM32F722xx
2915+
GenF7.menu.pnum.GENERIC_F722RCTX.build.variant=STM32F7xx/F722R(C-E)T_F730R8T_F732RET
2916+
2917+
# Generic F722RETx
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GenF7.menu.pnum.GENERIC_F722RETX=Generic F722RETx
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GenF7.menu.pnum.GENERIC_F722RETX.upload.maximum_size=524288
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GenF7.menu.pnum.GENERIC_F722RETX.upload.maximum_data_size=196608
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GenF7.menu.pnum.GENERIC_F722RETX.build.board=GENERIC_F722RETX
2922+
GenF7.menu.pnum.GENERIC_F722RETX.build.product_line=STM32F722xx
2923+
GenF7.menu.pnum.GENERIC_F722RETX.build.variant=STM32F7xx/F722R(C-E)T_F730R8T_F732RET
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# Generic F730R8Tx
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GenF7.menu.pnum.GENERIC_F730R8TX=Generic F730R8Tx
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GenF7.menu.pnum.GENERIC_F730R8TX.upload.maximum_size=65536
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GenF7.menu.pnum.GENERIC_F730R8TX.upload.maximum_data_size=196608
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GenF7.menu.pnum.GENERIC_F730R8TX.build.board=GENERIC_F730R8TX
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GenF7.menu.pnum.GENERIC_F730R8TX.build.product_line=STM32F730xx
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GenF7.menu.pnum.GENERIC_F730R8TX.build.variant=STM32F7xx/F722R(C-E)T_F730R8T_F732RET
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# Generic F732RETx
2934+
GenF7.menu.pnum.GENERIC_F732RETX=Generic F732RETx
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GenF7.menu.pnum.GENERIC_F732RETX.upload.maximum_size=524288
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GenF7.menu.pnum.GENERIC_F732RETX.upload.maximum_data_size=196608
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GenF7.menu.pnum.GENERIC_F732RETX.build.board=GENERIC_F732RETX
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GenF7.menu.pnum.GENERIC_F732RETX.build.product_line=STM32F732xx
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GenF7.menu.pnum.GENERIC_F732RETX.build.variant=STM32F7xx/F722R(C-E)T_F730R8T_F732RET
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# Generic F745ZETx
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GenF7.menu.pnum.GENERIC_F745ZETX=Generic F745ZETx
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GenF7.menu.pnum.GENERIC_F745ZETX.upload.maximum_size=524288

variants/STM32F7xx/F722R(C-E)T_F730R8T_F732RET/generic_clock.c

+52-2
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,58 @@
2121
*/
2222
WEAK void SystemClock_Config(void)
2323
{
24-
/* SystemClock_Config can be generated by STM32CubeMX */
25-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
25+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
26+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
27+
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/** Configure the main internal regulator output voltage
29+
*/
30+
__HAL_RCC_PWR_CLK_ENABLE();
31+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
32+
33+
/** Initializes the RCC Oscillators according to the specified parameters
34+
* in the RCC_OscInitTypeDef structure.
35+
*/
36+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
37+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
38+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 216;
43+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
44+
RCC_OscInitStruct.PLL.PLLQ = 9;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
46+
Error_Handler();
47+
}
48+
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/** Activate the Over-Drive mode
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*/
51+
if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
52+
Error_Handler();
53+
}
54+
55+
/** Initializes the CPU, AHB and APB buses clocks
56+
*/
57+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
59+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
60+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
61+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
62+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4;
63+
64+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
65+
Error_Handler();
66+
}
67+
68+
/** Initializes the peripherals clock
69+
*/
70+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_CLK48;
71+
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
72+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48;
73+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
74+
Error_Handler();
75+
}
2676
}
2777

2878
#endif /* ARDUINO_GENERIC_* */
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,184 @@
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/*
2+
******************************************************************************
3+
**
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** @file : LinkerScript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for F722R(C-E)T/F730R8T/F732RET Device from
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** STM32F7 series
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**
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** Set heap size, stack size and stack location according
12+
** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
19+
** of any kind.
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**
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******************************************************************************
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** @attention
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**
24+
** Copyright (c) 2022 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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******************************************************************************
32+
*/
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34+
/* Entry Point */
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ENTRY(Reset_Handler)
36+
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
39+
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
42+
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/* Memories definition */
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MEMORY
45+
{
46+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
47+
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
48+
}
49+
50+
/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
55+
{
56+
. = ALIGN(4);
57+
KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
59+
} >FLASH
60+
61+
/* The program code and other data into "FLASH" Rom type memory */
62+
.text :
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{
64+
. = ALIGN(4);
65+
*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
70+
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KEEP (*(.init))
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KEEP (*(.fini))
73+
74+
. = ALIGN(4);
75+
_etext = .; /* define a global symbols at end of code */
76+
} >FLASH
77+
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/* Constant data into "FLASH" Rom type memory */
79+
.rodata :
80+
{
81+
. = ALIGN(4);
82+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
85+
} >FLASH
86+
87+
.ARM.extab : {
88+
. = ALIGN(4);
89+
*(.ARM.extab* .gnu.linkonce.armextab.*)
90+
. = ALIGN(4);
91+
} >FLASH
92+
93+
.ARM : {
94+
. = ALIGN(4);
95+
__exidx_start = .;
96+
*(.ARM.exidx*)
97+
__exidx_end = .;
98+
. = ALIGN(4);
99+
} >FLASH
100+
101+
.preinit_array :
102+
{
103+
. = ALIGN(4);
104+
PROVIDE_HIDDEN (__preinit_array_start = .);
105+
KEEP (*(.preinit_array*))
106+
PROVIDE_HIDDEN (__preinit_array_end = .);
107+
. = ALIGN(4);
108+
} >FLASH
109+
110+
.init_array :
111+
{
112+
. = ALIGN(4);
113+
PROVIDE_HIDDEN (__init_array_start = .);
114+
KEEP (*(SORT(.init_array.*)))
115+
KEEP (*(.init_array*))
116+
PROVIDE_HIDDEN (__init_array_end = .);
117+
. = ALIGN(4);
118+
} >FLASH
119+
120+
.fini_array :
121+
{
122+
. = ALIGN(4);
123+
PROVIDE_HIDDEN (__fini_array_start = .);
124+
KEEP (*(SORT(.fini_array.*)))
125+
KEEP (*(.fini_array*))
126+
PROVIDE_HIDDEN (__fini_array_end = .);
127+
. = ALIGN(4);
128+
} >FLASH
129+
130+
/* Used by the startup to initialize data */
131+
_sidata = LOADADDR(.data);
132+
133+
/* Initialized data sections into "RAM" Ram type memory */
134+
.data :
135+
{
136+
. = ALIGN(4);
137+
_sdata = .; /* create a global symbol at data start */
138+
*(.data) /* .data sections */
139+
*(.data*) /* .data* sections */
140+
*(.RamFunc) /* .RamFunc sections */
141+
*(.RamFunc*) /* .RamFunc* sections */
142+
143+
. = ALIGN(4);
144+
_edata = .; /* define a global symbol at data end */
145+
146+
} >RAM AT> FLASH
147+
148+
/* Uninitialized data section into "RAM" Ram type memory */
149+
. = ALIGN(4);
150+
.bss :
151+
{
152+
/* This is used by the startup in order to initialize the .bss section */
153+
_sbss = .; /* define a global symbol at bss start */
154+
__bss_start__ = _sbss;
155+
*(.bss)
156+
*(.bss*)
157+
*(COMMON)
158+
159+
. = ALIGN(4);
160+
_ebss = .; /* define a global symbol at bss end */
161+
__bss_end__ = _ebss;
162+
} >RAM
163+
164+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
165+
._user_heap_stack :
166+
{
167+
. = ALIGN(8);
168+
PROVIDE ( end = . );
169+
PROVIDE ( _end = . );
170+
. = . + _Min_Heap_Size;
171+
. = . + _Min_Stack_Size;
172+
. = ALIGN(8);
173+
} >RAM
174+
175+
/* Remove information from the compiler libraries */
176+
/DISCARD/ :
177+
{
178+
libc.a ( * )
179+
libm.a ( * )
180+
libgcc.a ( * )
181+
}
182+
183+
.ARM.attributes 0 : { *(.ARM.attributes) }
184+
}

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