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1 parent 40f61c7 commit af7c166Copy full SHA for af7c166
coresimd/arm/armclang.rs
@@ -13,10 +13,9 @@
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/// - `0...65535` if you are compiling source as A32 code.
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/// - `0...255` if you are compiling source as T32 code.
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///
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+/// [ARM's documentation](https://developer.arm.com/docs/100067/latest/compiler-specific-intrinsics/__breakpoint-intrinsic)
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+///
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/// **NOTE** Due compiler limitations this function only supports the range `0...255` in A32 mode.
-// TODO support the extended range `0...65535` when compiling as A32 code (`cfg(not(target_feature =
-// "thumb-mode"))`). T32 mode (`cfg(target_feature = "thumb-mode")`) should continue to support the
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-// range `0...255`.
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#[cfg_attr(test, assert_instr(bkpt))]
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#[inline(always)]
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#[rustc_args_required_const(0)]
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