Prepare portable packed vector types for RFCs (#338)

* Prepare portable packed SIMD vector types for RFCs

This commit cleans up the implementation of the Portable Packed Vector Types
(PPTV), adds some new features, and makes some breaking changes.

The implementation is moved to `coresimd/src/ppvt` (they are
still exposed via `coresimd::simd`).

As before, the vector types of a certain width are implemented in the `v{width}`
submodules. The `macros.rs` file has been rewritten as an `api` module that
exposes the macros to implement each API.

It should now hopefully be really clear where each API is implemented, and which types
implement these APIs. It should also now be really clear which APIs are tested and how.

- boolean vectors of the form `b{element_size}x{number_of_lanes}`.
- reductions: arithmetic, bitwise, min/max, and boolean - only the facade,
  and a naive working implementation. These need to be implemented
  as `llvm.experimental.vector.reduction.{...}` but this needs rustc support first.
- FromBits trait analogous to `{f32,f64}::from_bits` that perform "safe" transmutes.
  Instead of writing `From::from`/`x.into()` (see below for breaking changes) now you write
  `FromBits::from_bits`/`x.into_bits()`.
- portable vector types implement `Default` and `Hash`
- tests for all portable vector types and all portable operations (~2000 new tests).
- (hopefully) comprehensive implementation of bitwise transmutes and lane-wise
  casts (before `From` and the `.as_...` methods where implemented "when they were needed".
- documentation for PPTV (not great yet, but better than nothing)
- conversions/transmutes from/to x86 architecture specific vector types

- `store/load` API has been replaced with `{store,load}_{aligned,unaligned}`
- `eq,ne,lt,le,gt,ge` APIs now return boolean vectors
- The `.as_{...}` methods have been removed. Lane-wise casts are now performed by `From`.
- `From` now perform casts (see above). It used to perform bitwise transmutes.
- `simd` vectors' `replace` method's result is now `#[must_use]`.

* enable backtrace and nocapture

* unalign load/store fail test by 1 byte

* update arm and aarch64 neon modules

* fix arm example

* fmt

* clippy and read example that rustfmt swallowed

* reductions should take self

* rename add/mul -> sum/product; delete other arith reductions

* clean up fmt::LowerHex impl

* revert incorret doc change

* make Hash equivalent to [T; lanes()]

* use travis_wait to increase timeout limit to 20 minutes

* remove travis_wait; did not help

* implement reductions on top of the llvm.experimental.vector.reduction intrinsics

* implement cmp for boolean vectors

* add missing eq impl file

* implement default

* rename llvm intrinsics

* fix aarch64 example error

* replace #[inline(always)] with #[inline]

* remove cargo clean from run.sh

* workaround broken product in aarch64

* make boolean vector constructors const fn

* fix more reductions on aarch64

* fix min/max reductions on aarch64

* remove whitespace

* remove all boolean vector types except for b8xN

* use a sum reduction fallback on aarch64

* disable llvm add reduction for aarch64

* rename the llvm intrinsics to use llvm names

* remove old macros.rs file

Author: gnzlbg

ci/run.sh

@@ -5,6 +5,8 @@ set -ex
 # Tests are all super fast anyway, and they fault often enough on travis that
 # having only one thread increases debuggability to be worth it.
 export RUST_TEST_THREADS=1
+export RUST_BACKTRACE=1
+export RUST_TEST_NOCAPTURE=1
 
 # FIXME(rust-lang-nursery/stdsimd#120) run-time feature detection for ARM Neon
 case ${TARGET} in

coresimd/aarch64/neon.rs

@@ -5,7 +5,7 @@
 #[cfg(test)]
 use stdsimd_test::assert_instr;
 use coresimd::simd_llvm::simd_add;
-use coresimd::v128::f64x2;
+use coresimd::simd::*;
 
 /// Vector add.
 #[inline]

coresimd/arm/neon.rs

@@ -4,8 +4,8 @@
 use stdsimd_test::assert_instr;
 
 use coresimd::simd_llvm::simd_add;
-use coresimd::v64::*;
-use coresimd::v128::*;
+use coresimd::simd::*;
+use convert::From;
 
 /// Vector add.
 #[inline]
@@ -140,8 +140,8 @@ pub unsafe fn vaddq_f32(a: f32x4, b: f32x4) -> f32x4 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(saddl))]
 pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
-    let a = a.as_i16x8();
-    let b = b.as_i16x8();
+    let a = i16x8::from(a);
+    let b = i16x8::from(b);
     simd_add(a, b)
 }
 
@@ -150,8 +150,8 @@ pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(saddl))]
 pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
-    let a = a.as_i32x4();
-    let b = b.as_i32x4();
+    let a = i32x4::from(a);
+    let b = i32x4::from(b);
     simd_add(a, b)
 }
 
@@ -160,8 +160,8 @@ pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(saddl))]
 pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
-    let a = a.as_i64x2();
-    let b = b.as_i64x2();
+    let a = i64x2::from(a);
+    let b = i64x2::from(b);
     simd_add(a, b)
 }
 
@@ -170,8 +170,8 @@ pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uaddl))]
 pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
-    let a = a.as_u16x8();
-    let b = b.as_u16x8();
+    let a = u16x8::from(a);
+    let b = u16x8::from(b);
     simd_add(a, b)
 }
 
@@ -180,8 +180,8 @@ pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uaddl))]
 pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
-    let a = a.as_u32x4();
-    let b = b.as_u32x4();
+    let a = u32x4::from(a);
+    let b = u32x4::from(b);
     simd_add(a, b)
 }
 
@@ -190,8 +190,8 @@ pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uaddl))]
 pub unsafe fn vaddl_u32(a: u32x2, b: u32x2) -> u64x2 {
-    let a = a.as_u64x2();
-    let b = b.as_u64x2();
+    let a = u64x2::from(a);
+    let b = u64x2::from(b);
     simd_add(a, b)
 }