[arm] bitwise manipulation instructions

Author: gnzlbg

asm/armv6_none_rev.asm

@@ -0,0 +1,3 @@
+rev_u32:
+  rev	r0, r0
+  bx	lr

asm/armv6_none_rev.rs

@@ -0,0 +1,6 @@
+extern crate stdsimd;
+
+#[no_mangle]
+pub fn rev_u32(x: u32) -> u32 {
+    stdsimd::vendor::_rev_u32(x)
+}

asm/armv7_none_rbit.asm

@@ -0,0 +1,3 @@
+rbit_u32:
+  rbit	r0, r0
+  bx	lr

asm/armv7_none_rbit.rs

@@ -0,0 +1,6 @@
+extern crate stdsimd;
+
+#[no_mangle]
+pub fn rbit_u32(x: u32) -> u32 {
+    stdsimd::vendor::_rbit_u32(x)
+}

asm/armv8_none_cls.asm

@@ -0,0 +1,17 @@
+;; Should be:
+;; cls_u32:
+;;   cls w0, w0
+;;   ret
+;; cls_u64:
+;;   cls x0, x0
+;;   ret
+;; But due to LLVM Bug: https://bugs.llvm.org/show_bug.cgi?id=31802
+;; (stdsimd issue #30) is:
+cls_u32:
+  mvn	 w8, w0
+  clz	w0, w8
+  ret
+cls_u64:
+  mvn	 x8, x0
+  clz	x0, x8
+  ret

asm/armv8_none_cls.rs

@@ -0,0 +1,11 @@
+extern crate stdsimd;
+
+#[no_mangle]
+pub fn cls_u32(x: u32) -> u32 {
+    stdsimd::vendor::_cls_u32(x)
+}
+
+#[no_mangle]
+pub fn cls_u64(x: u64) -> u64 {
+    stdsimd::vendor::_cls_u64(x)
+}

asm/armv8_none_rbit.asm

@@ -0,0 +1,6 @@
+rbit_u32:
+  rbit	w0, w0
+  ret
+rbit_u64:
+  rbit	x0, x0
+  ret

asm/armv8_none_rbit.rs

@@ -0,0 +1,11 @@
+extern crate stdsimd;
+
+#[no_mangle]
+pub fn rbit_u32(x: u32) -> u32 {
+    stdsimd::vendor::_rbit_u32(x)
+}
+
+#[no_mangle]
+pub fn rbit_u64(x: u64) -> u64 {
+    stdsimd::vendor::_rbit_u64(x)
+}

check_asm.py

@@ -12,7 +12,8 @@
 extern_crate = None
 
 def arm_triplet(arch) :
-    triples = { 'armv7' : 'armv7-unknown-linux-gnueabihf',
+    triples = { 'armv6': 'arm-unknown-linux-gnueabihf',
+                'armv7' : 'armv7-unknown-linux-gnueabihf',
                 'armv8' : 'aarch64-unknown-linux-gnu' }
     return triples[arch]
 
@@ -57,14 +58,14 @@ def compile_file(file):
     cargo_args = 'cargo rustc --verbose --release -- -C panic=abort '
     if file.feature:
         cargo_args = cargo_args + '-C target-feature=+{}'.format(file.feature)
-    if file.arch == 'armv7' or file.arch == 'armv8':
+    if file.arch == 'armv6' or file.arch == 'armv7' or file.arch == 'armv8':
         cargo_args = cargo_args + '--target={}'.format(arm_triplet(file.arch))
     call(str(cargo_args))
 
     rustc_args = 'rustc --verbose -C opt-level=3 -C panic="abort" --extern %s=target/release/lib%s.rlib --crate-type lib' % (extern_crate, extern_crate);
     if file.feature:
         rustc_args = rustc_args + ' -C target-feature=+{}'.format(file.feature)
-    if file.arch == 'armv7' or file.arch == 'armv8':
+    if file.arch == 'armv6' or file.arch == 'armv7' or file.arch == 'armv8':
         rustc_args = rustc_args + ' --target={}'.format(arm_triplet(file.arch))
     rustc_args_asm = rustc_args + ' --emit asm {} -o {}'.format(file.path_rs, file.path_asm_output)
     call(rustc_args_asm)
@@ -83,9 +84,9 @@ def diff_files(rustc_output, asm_snippet):
 
     # remove all empty lines and lines starting with "."
     rustc_output_lines = [l.strip() for l in rustc_output_lines]
-    rustc_output_lines = [l for l in rustc_output_lines if not l.startswith(".") and not len(l) == 0]
+    rustc_output_lines = [l for l in rustc_output_lines if not l.startswith(".") and not len(l) == 0 and not l.startswith(";;")]
     asm_snippet_lines = [l.strip() for l in asm_snippet_lines]
-    asm_snippet_lines = [l for l in asm_snippet_lines if not l.startswith(".") and not len(l) == 0]
+    asm_snippet_lines = [l for l in asm_snippet_lines if not l.startswith(".") and not len(l) == 0 and not l.startswith(";;")]
 
     results_differ = False
 

src/arm/mod.rs

@@ -0,0 +1,10 @@
+//! ARM intrinsics.
+pub use self::v6::*;
+pub use self::v7::*;
+#[cfg(target_arch = "aarch64")]
+pub use self::v8::*;
+
+mod v6;
+mod v7;
+#[cfg(target_arch = "aarch64")]
+mod v8;

src/arm/v6.rs

@@ -0,0 +1,22 @@
+//! ARMv6 intrinsics.
+//!
+//! The reference is [ARMv6-M Architecture Reference
+//! Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0419c/index.html).
+
+/// Reverse the order of the bytes.
+#[inline(always)]
+pub fn _rev_u8(x: u8) -> u8 {
+    x.swap_bytes() as u8
+}
+
+/// Reverse the order of the bytes.
+#[inline(always)]
+pub fn _rev_u16(x: u16) -> u16 {
+    x.swap_bytes() as u16
+}
+
+/// Reverse the order of the bytes.
+#[inline(always)]
+pub fn _rev_u32(x: u32) -> u32 {
+    x.swap_bytes() as u32
+}

src/arm/v7.rs

@@ -0,0 +1,36 @@
+//! ARMv7 intrinsics.
+//!
+//! The reference is [ARMv7-M Architecture Reference Manual (Issue
+//! E.b)](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.b/index.html).
+
+pub use super::v6::*;
+
+/// Count Leading Zeros.
+#[inline(always)]
+pub fn _clz_u8(x: u8) -> u8 {
+    x.leading_zeros() as u8
+}
+
+/// Count Leading Zeros.
+#[inline(always)]
+pub fn _clz_u16(x: u16) -> u16 {
+    x.leading_zeros() as u16
+}
+
+/// Count Leading Zeros.
+#[inline(always)]
+pub fn _clz_u32(x: u32) -> u32 {
+    x.leading_zeros() as u32
+}
+
+#[allow(dead_code)]
+extern "C" {
+    #[link_name="llvm.bitreverse.i32"]
+    fn rbit_u32(i: i32) -> i32;
+}
+
+/// Reverse the bit order.
+#[inline(always)]
+pub fn _rbit_u32(x: u32) -> u32 {
+    unsafe { rbit_u32(x as i32) as u32 }
+}

src/arm/v8.rs

@@ -0,0 +1,47 @@
+//! ARMv8 intrinsics.
+//!
+//! The reference is [ARMv8-A Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.k_10775/index.html).
+
+pub use super::v7::*;
+
+/// Reverse the order of the bytes.
+#[inline(always)]
+pub fn _rev_u64(x: u64) -> u64 {
+    x.swap_bytes() as u64
+}
+
+/// Count Leading Zeros.
+#[inline(always)]
+pub fn _clz_u64(x: u64) -> u64 {
+    x.leading_zeros() as u64
+}
+
+#[allow(dead_code)]
+extern "C" {
+    #[link_name="llvm.bitreverse.i64"]
+    fn rbit_u64(i: i64) -> i64;
+}
+
+/// Reverse the bit order.
+#[inline(always)]
+pub fn _rbit_u64(x: u64) -> u64 {
+    unsafe { rbit_u64(x as i64) as u64 }
+}
+
+/// Counts the leading most significant bits set.
+///
+/// When all bits of the operand are set it returns the size of the operand in
+/// bits.
+#[inline(always)]
+pub fn _cls_u32(x: u32) -> u32 {
+    u32::leading_zeros(!x) as u32
+}
+
+/// Counts the leading most significant bits set.
+///
+/// When all bits of the operand are set it returns the size of the operand in
+/// bits.
+#[inline(always)]
+pub fn _cls_u64(x: u64) -> u64 {
+    u64::leading_zeros(!x) as u64
+}

src/lib.rs

@@ -16,6 +16,9 @@ pub mod simd {
 pub mod vendor {
     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
     pub use x86::*;
+
+    #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+    pub use arm::*;
 }
 
 #[macro_use]
@@ -27,3 +30,6 @@ mod v512;
 mod v64;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 mod x86;
+
+#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+ mod arm;