Skip to content

Commit c96634a

Browse files
committed
Fix mem op= mem bug in trans.ml (via not terribly good fix). Closes #111.
1 parent 2c24f70 commit c96634a

File tree

3 files changed

+27
-1
lines changed

3 files changed

+27
-1
lines changed

src/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -429,6 +429,7 @@ TEST_XFAILS_LLVM := $(addprefix test/run-pass/, \
429429
generic-tag.rs \
430430
import.rs \
431431
inner-module.rs \
432+
iter-range.rs \
432433
large-records.rs \
433434
lazy-and-or.rs \
434435
lazy-init.rs \

src/boot/me/trans.ml

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4343,8 +4343,15 @@ let trans_visitor
43434343
trans_vec_append dst_cell dst_ty src_oper (atom_type cx a_src)
43444344
| _ ->
43454345
let (dst_cell, _) = deref_ty DEREF_none false dst_cell dst_ty in
4346+
let bits = Il.operand_bits word_bits src_oper in
4347+
(*
4348+
* FIXME: X86-ism going via a vreg; mem op= mem doesn't work and
4349+
* IL lacks sufficient brains to cope just now.
4350+
*)
4351+
let src = Il.Reg (Il.next_vreg (emitter()), Il.ValTy bits) in
43464352
let op = trans_binop binop in
4347-
emit (Il.binary op dst_cell (Il.Cell dst_cell) src_oper);
4353+
mov src src_oper;
4354+
emit (Il.binary op dst_cell (Il.Cell dst_cell) (Il.Cell src));
43484355

43494356

43504357
and trans_call id dst flv args =

src/test/run-pass/iter-range.rs

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
iter range(int a, int b) -> int {
2+
check (a < b);
3+
4+
let int i = a;
5+
while (i < b) {
6+
put i;
7+
i += 1;
8+
}
9+
}
10+
11+
fn main() {
12+
let int sum = 0;
13+
for each (int x in range(0, 100)) {
14+
sum += x;
15+
}
16+
17+
log sum;
18+
}

0 commit comments

Comments
 (0)