Merge pull request #18 from Disasm/riscv-lto-upstream

Unlock ThinLTO for RISC-V (second try)

Author: alexcrichton

lld/ELF/InputFiles.cpp

@@ -1086,6 +1086,9 @@ static uint8_t getBitcodeMachineKind(StringRef Path, const Triple &T) {
   case Triple::ppc64:
   case Triple::ppc64le:
     return EM_PPC64;
+  case Triple::riscv32:
+  case Triple::riscv64:
+    return EM_RISCV;
   case Triple::x86:
     return T.isOSIAMCU() ? EM_IAMCU : EM_386;
   case Triple::x86_64:

lld/test/ELF/lto/riscv32.ll

@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-elf"
+
+define void @f() {
+  ret void
+}

lld/test/ELF/lto/riscv64.ll

@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-elf"
+
+define void @f() {
+  ret void
+}