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//! why, because these methods can't return before receiving all the read data. However it's still technically possible
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//! for them to return before the bus is idle. For example, assuming SPI mode 0, the last bit is sampled on the first (rising) edge
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//! of SCK, at which point a method could return, but the second (falling) SCK edge still has to happen before the bus is idle.
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+ //!
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+ //! # CS-to-clock delays
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+ //!
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+ //! Many chips require a minimum delay between asserting CS and the first SCK edge, and the last SCK edge and deasserting CS.
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+ //! Drivers should *NOT* use [`Operation::DelayNs`] for this, they should instead document that the user should configure the
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+ //! delays when creating the `SpiDevice` instance, same as they have to configure the SPI frequency and mode. This has a few advantages:
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+ //!
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+ //! - Allows implementations that use hardware-managed CS to program the delay in hardware
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+ //! - Allows the end user more flexibility. For example, they can choose to not configure any delay if their MCU is slow
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+ //! enough to "naturally" do the delay (very common if the delay is in the order of nanoseconds).
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use core:: fmt:: Debug ;
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