Update only the ORRWrs branch

Author: dianqk

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -9180,15 +9180,12 @@ void AArch64InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
 
 std::optional<DestSourcePair>
 AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+
   // AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
   // and zero immediate operands used as an alias for mov instruction.
-  bool OpIsORRWrs = MI.getOpcode() == AArch64::ORRWrs;
-  bool OpIsORRXrs = MI.getOpcode() == AArch64::ORRXrs;
-  if (!(OpIsORRWrs || OpIsORRXrs) || MI.getOperand(3).getImm() != 0x0)
-    return std::nullopt;
-  Register Reg1 = MI.getOperand(1).getReg();
-
-  if (OpIsORRWrs && Reg1 == AArch64::WZR) {
+  if (MI.getOpcode() == AArch64::ORRWrs &&
+      MI.getOperand(1).getReg() == AArch64::WZR &&
+      MI.getOperand(3).getImm() == 0x0) {
     Register Reg0 = MI.getOperand(0).getReg();
     // ORRWrs is copy instruction when there's no implicit def of the X
     // register.
@@ -9204,9 +9201,10 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
     return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
   }
 
-  if (OpIsORRXrs && Reg1 == AArch64::XZR) {
+  if (MI.getOpcode() == AArch64::ORRXrs &&
+      MI.getOperand(1).getReg() == AArch64::XZR &&
+      MI.getOperand(3).getImm() == 0x0)
     return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
-  }
 
   return std::nullopt;
 }