From ddc95d9348454c2a4934ec08f6b96667d87b04b1 Mon Sep 17 00:00:00 2001
From: Gonzalo Brusco <gonzabrusco@gmail.com>
Date: Thu, 27 Mar 2025 16:41:24 -0300
Subject: [PATCH 01/35] Add an option to force IDF's default UART clock source

---
 Kconfig.projbuild            | 11 +++++++++++
 cores/esp32/esp32-hal-uart.c |  8 +++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/Kconfig.projbuild b/Kconfig.projbuild
index 9966463f8c1..120dbf8a701 100644
--- a/Kconfig.projbuild
+++ b/Kconfig.projbuild
@@ -118,6 +118,17 @@ config ARDUINO_SERIAL_EVENT_TASK_PRIORITY
     help
         Select at what priority you want the Serial Event task to run.
 
+config ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
+    bool "Force IDF default UART clock source"
+    default "n"
+    help
+        Overrides Arduino's automatic UART clock selection with the default clock from IDF (clk_tree_defs.h).
+        By default, Arduino optimizes the UART clock automatically: XTAL clock for C2, S3, C3, C6, H2, P4 and 
+        REF_TICK (<250k baud) or APB (>250k baud) for ESP32, S2.
+        Enable this option only if you need to force IDF's default clock instead of Arduino's optimized settings.
+        It is generally recommended to leave this disabled unless specifically required.
+        Note: This configuration is not applicable to the low-power (LP) UART controller.
+
 choice ARDUINO_UDP_RUNNING_CORE
     bool "Core on which Arduino's UDP is running"
     default ARDUINO_UDP_RUN_CORE0
diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 75e2da013ea..a47d0e16831 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -670,6 +670,11 @@ uart_t *uartBegin(
   } else
 #endif
   {
+#if CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
+    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+    uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
+    log_v("Setting UART%d to use DEFAULT clock", uart_nr);
+#else
     // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
     // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
@@ -684,9 +689,10 @@ uart_t *uartBegin(
       log_v("Setting UART%d to use APB clock", uart_nr);
     }
 #else
-    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6
+    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
     uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
     log_v("Setting UART%d to use DEFAULT clock", uart_nr);
+#endif
 #endif
   }
 

From f64ded24ebcf8ce036115c40b5171462fbd1842a Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 11:21:06 -0300
Subject: [PATCH 02/35] feat(uart): adds function to set clock source

---
 cores/esp32/HardwareSerial.h | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index b1f6df17724..80988ed91d1 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -96,6 +96,30 @@ typedef enum {
   UART_PARITY_ERROR
 } hardwareSerial_error_t;
 
+  typedef enum {
+#if SOC_UART_SUPPORT_APB_CLK
+    UART_CLK_SRC_APB = SOC_MOD_CLK_APB,
+#endif
+#if SOC_UART_SUPPORT_PLL_F40M_CLK
+    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F40M,
+#endif
+#if SOC_UART_SUPPORT_PLL_F80M_CLK
+    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F80M,
+#endif
+#if CONFIG_IDF_TARGET_ESP32H2
+    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F48M,
+#endif
+#if SOC_UART_SUPPORT_XTAL_CLK
+    UART_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
+#endif
+#if SOC_UART_SUPPORT_RTC_CLK
+    UART_CLK_SRC_RTC_FAST = SOC_MOD_CLK_RC_FAST,
+#endif
+#if SOC_UART_SUPPORT_REF_TICK
+    UART_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK,
+#endif
+} SerialClkSrc;
+
 #ifndef ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
 #ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
 #define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE 2048
@@ -344,9 +368,18 @@ class HardwareSerial : public Stream {
   //    UART_MODE_RS485_COLLISION_DETECT = 0x03    mode: RS485 collision detection UART mode (used for test purposes)
   //    UART_MODE_RS485_APP_CTRL         = 0x04    mode: application control RS485 UART mode (used for test purposes)
   bool setMode(SerialMode mode);
+  // Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect.
+  // Not all clock source are available to every SoC. The compatible option are listed here:
+  // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+  // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
+  // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+  // UART_CLK_SRC_RTC_FAST     :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+  // UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
+  // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
+  // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
+  bool setClockSource(SerialClkSrc clkSrc);
   size_t setRxBufferSize(size_t new_size);
   size_t setTxBufferSize(size_t new_size);
-
 protected:
   uint8_t _uart_nr;
   uart_t *_uart;

From baced536eed4fdb06d1ab19474fdc5ce9375bede Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 11:37:44 -0300
Subject: [PATCH 03/35] feat(uart): add uart clock source selection method

---
 cores/esp32/HardwareSerial.cpp | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 76135691411..eac5b15c15c 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -607,6 +607,20 @@ bool HardwareSerial::setMode(SerialMode mode) {
   return uartSetMode(_uart, mode);
 }
 
+// Sets the UART Clock Source based on the compatible SoC options
+// This method must be called before starting UART using begin(), otherwise it won't have any effect.
+// Clock Source Options are:
+// UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+// UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
+// UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_CLK_SRC_RTC_FAST     :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
+// Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
+// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
+bool setClockSource(SerialClkSrc clkSrc) {
+  return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
+}
+
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
 // LP UART has FIFO of 16 bytes
 size_t HardwareSerial::setRxBufferSize(size_t new_size) {

From 36efd181418741102738520fb6ab6cbcadfd47d3 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 11:46:30 -0300
Subject: [PATCH 04/35] feat(uart): add uart hall function to set the uart
 clock source

---
 cores/esp32/esp32-hal-uart.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h
index 4d686fdd23d..0a84e39d64f 100644
--- a/cores/esp32/esp32-hal-uart.h
+++ b/cores/esp32/esp32-hal-uart.h
@@ -97,6 +97,18 @@ bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t thr
 //    UART_MODE_RS485_APP_CTRL         = 0x04    mode: application control RS485 UART mode (used for test purposes)
 bool uartSetMode(uart_t *uart, uart_mode_t mode);
 
+// Used to set the UART clock source mode. It must be set before calling uartBegin(), otherwise it won't have any effect.
+// Not all clock source are available to every SoC. The compatible option are listed here:
+// UART_SCLK_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+// UART_SCLK_PLL_F80M     :: ESP32-C5, ESP32-C6, ESP32-C61 and ESP32-P4
+// UART_SCLK_PLL_F40M     :: ESP32-C2
+// UART_SCLK_PLL_F48M     :: ESP32-H2
+// UART_SCLK_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_SCLK_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_SCLK_REF_TICK     :: ESP32 and ESP32-S2
+// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only LP_UART_SCLK_LP_FAST (RTC_FAST) or LP_UART_SCLK_XTAL_D2 (XTAL/2) as Clock Source
+bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc);
+
 void uartStartDetectBaudrate(uart_t *uart);
 unsigned long uartDetectBaudrate(uart_t *uart);
 

From d86057255075463e86a459b356249d1a6845e482 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 12:23:35 -0300
Subject: [PATCH 05/35] feat(uart): add function to set the uart clock source

---
 cores/esp32/esp32-hal-uart.c | 92 ++++++++++++++++++++++++++----------
 1 file changed, 66 insertions(+), 26 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index a47d0e16831..65f324cad97 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -58,6 +58,7 @@ struct uart_struct_t {
   uint16_t _rx_buffer_size, _tx_buffer_size;  // UART RX and TX buffer sizes
   bool _inverted;                             // UART inverted signal
   uint8_t _rxfifo_full_thrhd;                 // UART RX FIFO full threshold
+  int8_t _uart_clock_source;                  // UART Clock Source used when it is started using uartBegin()
 };
 
 #if CONFIG_DISABLE_HAL_LOCKS
@@ -66,21 +67,21 @@ struct uart_struct_t {
 #define UART_MUTEX_UNLOCK()
 
 static uart_t _uart_bus_array[] = {
-  {0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #if SOC_UART_NUM > 1
-  {1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 2
-  {2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 3
-  {3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 4
-  {4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 5
-  {5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 };
 
@@ -95,21 +96,21 @@ static uart_t _uart_bus_array[] = {
   xSemaphoreGive(uart->lock)
 
 static uart_t _uart_bus_array[] = {
-  {NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #if SOC_UART_NUM > 1
-  {NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 2
-  {NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 3
-  {NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 4
-  {NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 #if SOC_UART_NUM > 5
-  {NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
+  {NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
 #endif
 };
 
@@ -665,8 +666,12 @@ uart_t *uartBegin(
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
   if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
-    uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
-    log_v("Setting UART%d to use LP clock", uart_nr);
+    if (uart->_uart_clock_source > 0) {
+      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+    } else {
+      uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
+    }
+    log_v("Setting UART%d to use LP clock (%d) ", uart_nr, uart_config.lp_source_clk);
   } else
 #endif
   {
@@ -675,25 +680,29 @@ uart_t *uartBegin(
     uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
     log_v("Setting UART%d to use DEFAULT clock", uart_nr);
 #else
+    if (uart->_uart_clock_source > 0) {
+      uart_config.source_clk = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+    } else {    
     // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
     // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
-    uart_config.source_clk = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
-    log_v("Setting UART%d to use XTAL clock", uart_nr);
+      uart_config.source_clk = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
+      log_v("Setting UART%d to use XTAL clock", uart_nr);
 #elif SOC_UART_SUPPORT_REF_TICK
-    if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
-      uart_config.source_clk = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
-      log_v("Setting UART%d to use REF_TICK clock", uart_nr);
-    } else {
-      uart_config.source_clk = UART_SCLK_APB;  // baudrate may change with the APB Frequency!
-      log_v("Setting UART%d to use APB clock", uart_nr);
-    }
+      if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
+        uart_config.source_clk = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
+        log_v("Setting UART%d to use REF_TICK clock", uart_nr);
+      } else {
+        uart_config.source_clk = UART_SCLK_APB;  // baudrate may change with the APB Frequency!
+        log_v("Setting UART%d to use APB clock", uart_nr);
+      }
 #else
-    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
-    uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
-    log_v("Setting UART%d to use DEFAULT clock", uart_nr);
+      // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+      uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
+      log_v("Setting UART%d to use DEFAULT clock", uart_nr);
 #endif
 #endif
+    }
   }
 
   UART_MUTEX_LOCK();
@@ -1090,6 +1099,37 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode) {
   return retCode;
 }
 
+// this function will set the uart clock source 
+// it must be called before uartBegin(), otherwise it won't change any thing.
+bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
+  if (uart == NULL) {
+    return false;
+  }
+  if (uart_is_driver_installed(uart->num)) {
+    log_e("No Clock Source change was done. This function must be called before beginning UART%d.", uart->num);
+    return false;
+  }
+#if SOC_UART_LP_NUM >= 1
+  if (uart->num >  >= SOC_UART_HP_NUM) {
+    switch (clkSrc) {
+      case UART_SCLK_XTAL:
+        uart->_uart_clock_source = SOC_MOD_CLK_XTAL_D2;
+        break;
+      case UART_SCLK_RTC:
+        uart->_uart_clock_source = SOC_MOD_CLK_RTC_FAST;
+        break;
+      default:
+        uart->_uart_clock_source = -1;
+    }
+  } else
+#else
+  {
+    uart->_uart_clock_source = clkSrc;
+  }
+#endif
+  return true;
+}
+
 void uartSetDebug(uart_t *uart) {
   // LP UART is not supported for debug
   if (uart == NULL || uart->num >= SOC_UART_HP_NUM) {

From 667dcac3fd242a49ef72a4f14c2575ed7a681e5b Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 13:05:00 -0300
Subject: [PATCH 06/35] feat(uart): set clock source as necessary

---
 cores/esp32/esp32-hal-uart.c | 75 +++++++++++++++++++++++++++---------
 1 file changed, 57 insertions(+), 18 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 65f324cad97..edd30818efd 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -668,20 +668,22 @@ uart_t *uartBegin(
   if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
       uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
     } else {
       uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
+      log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
-    log_v("Setting UART%d to use LP clock (%d) ", uart_nr, uart_config.lp_source_clk);
   } else
-#endif
+#endif // SOC_UART_LP_NUM >= 1
   {
 #if CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
     // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
     uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
     log_v("Setting UART%d to use DEFAULT clock", uart_nr);
 #else
-    if (uart->_uart_clock_source > 0) {
+    if (uart->_uart_clock_source >= 0) {
       uart_config.source_clk = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
     } else {    
     // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
     // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
@@ -700,9 +702,9 @@ uart_t *uartBegin(
       // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
       uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
       log_v("Setting UART%d to use DEFAULT clock", uart_nr);
-#endif
-#endif
+#endif // SOC_UART_SUPPORT_XTAL_CLK
     }
+#endif // CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
   }
 
   UART_MUTEX_LOCK();
@@ -731,6 +733,7 @@ uart_t *uartBegin(
     uart->_tx_buffer_size = tx_buffer_size;
     uart->has_peek = false;
     uart->peek_byte = 0;
+    uart->_uart_clock_source = uart_config.source_clk;
   }
   UART_MUTEX_UNLOCK();
 
@@ -990,22 +993,58 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
     return false;
   }
   bool retCode = true;
-  UART_MUTEX_LOCK();
-#if SOC_UART_SUPPORT_XTAL_CLK  // ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2 and ESP32-P4
-  soc_module_clk_t newClkSrc = UART_SCLK_XTAL;
+  soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
+  uint8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
-  if (uart->num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
-    newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
+  if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+    if (uart->_uart_clock_source > 0) {
+      newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
+    } else {
+      newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
+      log_v("Setting UART%d to Default LP clock source", uart->num);
+    }
+  } else 
+#endif // SOC_UART_LP_NUM >= 1
+  {
+#if CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
+    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+    // newClkSrc already set in the variable declaration
+    log_v("Setting UART%d to use DEFAULT clock", uart->num);
+#else
+    if (uart->_uart_clock_source >= 0) {
+      newClkSrc = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
+    } else {    
+    // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+    // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+#if SOC_UART_SUPPORT_XTAL_CLK
+      newClkSrc = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
+      log_v("Setting UART%d to use XTAL clock", uart->num);
+#elif SOC_UART_SUPPORT_REF_TICK
+      if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
+        newClkSrc = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
+        log_v("Setting UART%d to use REF_TICK clock", uart->num);
+      } else {
+        newClkSrc = UART_SCLK_APB;  // baudrate may change with the APB Frequency!
+        log_v("Setting UART%d to use APB clock", uart->num);
+      }
+#else
+      // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+      // using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration
+      log_v("Setting UART%d to use DEFAULT clock", uart->num);
+#endif // SOC_UART_SUPPORT_XTAL_CLK
+    }
+#endif // CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
   }
-#endif
-  // ESP32-P4 demands an atomic operation for setting the clock source
-  HP_UART_SRC_CLK_ATOMIC() {
-    uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
+  UART_MUTEX_LOCK();
+  // if necessary, set the correct UART Clock Source before changing the baudrate
+  if (previousClkSrc != newClkSrc) {
+    HP_UART_SRC_CLK_ATOMIC() {
+      uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
+    }
+    uart->_uart_clock_source = newClkSrc;
   }
-#else  // ESP32, ESP32-S2
-  soc_module_clk_t newClkSrc = baud_rate <= REF_TICK_BAUDRATE_LIMIT ? SOC_MOD_CLK_REF_TICK : SOC_MOD_CLK_APB;
-  uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
-#endif
   if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) {
     log_v("Setting UART%d baud rate to %ld.", uart->num, baud_rate);
     uart->_baudrate = baud_rate;

From 720747f001fcec5f3f6c80abe44bec0f05140398 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 13:11:59 -0300
Subject: [PATCH 07/35] fix(uart): missing class qualifier declaration

---
 cores/esp32/HardwareSerial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index eac5b15c15c..2c5a091e08b 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -617,7 +617,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
-bool setClockSource(SerialClkSrc clkSrc) {
+bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
   return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
 }
 

From e9bf067ec1ce781923efb770ad90f63a17c218d3 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 13:22:50 -0300
Subject: [PATCH 08/35] fix(uart): fixing a typo and non LP UART SoC clk src
 setting

---
 cores/esp32/esp32-hal-uart.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index edd30818efd..7a029029e6c 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -996,7 +996,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
   uint8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
-  if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+  if (uart->num >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
       newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
@@ -1149,7 +1149,7 @@ bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
     return false;
   }
 #if SOC_UART_LP_NUM >= 1
-  if (uart->num >  >= SOC_UART_HP_NUM) {
+  if (uart->num >= SOC_UART_HP_NUM) {
     switch (clkSrc) {
       case UART_SCLK_XTAL:
         uart->_uart_clock_source = SOC_MOD_CLK_XTAL_D2;
@@ -1161,11 +1161,10 @@ bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
         uart->_uart_clock_source = -1;
     }
   } else
-#else
+#endif
   {
     uart->_uart_clock_source = clkSrc;
   }
-#endif
   return true;
 }
 

From 858c0c2c744e76b6ec72587304f6487a64f35a40 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 13:27:39 -0300
Subject: [PATCH 09/35] fix(uart): variable name, typo error

---
 cores/esp32/esp32-hal-uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 7a029029e6c..3e72693c7f9 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -1022,7 +1022,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
       newClkSrc = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
       log_v("Setting UART%d to use XTAL clock", uart->num);
 #elif SOC_UART_SUPPORT_REF_TICK
-      if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
+      if (baud_rate <= REF_TICK_BAUDRATE_LIMIT) {
         newClkSrc = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
         log_v("Setting UART%d to use REF_TICK clock", uart->num);
       } else {

From a7c605424d3d0f266d8b87b931e49011015b628d Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 13:56:38 -0300
Subject: [PATCH 10/35] fix(uart): retores previous identation reducing diff
 load

---
 cores/esp32/esp32-hal-uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 3e72693c7f9..9b6e17010ef 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -996,7 +996,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
   uint8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
-  if (uart->num >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+  if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
       newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);

From d8526f83b95e197597090d490694d092cf93e6e1 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:00:33 -0300
Subject: [PATCH 11/35] feat(uart): apply
 CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE to LP UART

---
 cores/esp32/esp32-hal-uart.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 9b6e17010ef..1df5804474b 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -666,10 +666,13 @@ uart_t *uartBegin(
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
   if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+#if !(CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE)
     if (uart->_uart_clock_source > 0) {
       uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
-    } else {
+    } else 
+#endif
+    {
       uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
@@ -997,10 +1000,13 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   uint8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+#if !(CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE)
     if (uart->_uart_clock_source > 0) {
       newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
-    } else {
+    } else
+#endif
+    {
       newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart->num);
     }

From 513d67fc7c8cf6b17d2598a6f4014d63cc12e354 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:20:26 -0300
Subject: [PATCH 12/35] feat(uart): adds option for UART_CLK_SRC_DEFAULT

---
 cores/esp32/HardwareSerial.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 80988ed91d1..4ca2546aa08 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -97,6 +97,7 @@ typedef enum {
 } hardwareSerial_error_t;
 
   typedef enum {
+    UART_CLK_SRC_DEFAULT = -1,
 #if SOC_UART_SUPPORT_APB_CLK
     UART_CLK_SRC_APB = SOC_MOD_CLK_APB,
 #endif

From 0fe2b6019af0e209648525eabae60a32cb828772 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:25:57 -0300
Subject: [PATCH 13/35] feat(uart): adds option for setting default uart clock
 source from IDF

---
 cores/esp32/HardwareSerial.cpp | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 2c5a091e08b..26b6ffac813 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -610,6 +610,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Sets the UART Clock Source based on the compatible SoC options
 // This method must be called before starting UART using begin(), otherwise it won't have any effect.
 // Clock Source Options are:
+// UART_CLK_SRC_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
 // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
 // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
 // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
@@ -618,7 +619,11 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-  return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
+  if (clkSrc == UART_CLK_SRC_DEFAULT) {
+    return uartSetClockSource(_uart, (uart_sclk_t) UART_SCLK_DEFAULT);
+  } else {
+    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
+  }
 }
 
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.

From 326469317cbd131d53b7ef3aee1212e19c96cf11 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:27:39 -0300
Subject: [PATCH 14/35] feat(uart): documents UART_CLK_SRC_DEFAULT as option in
 header file

---
 cores/esp32/HardwareSerial.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 4ca2546aa08..22f9f6cd318 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -371,6 +371,7 @@ class HardwareSerial : public Stream {
   bool setMode(SerialMode mode);
   // Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect.
   // Not all clock source are available to every SoC. The compatible option are listed here:
+  // UART_CLK_SRC_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
   // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
   // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
   // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4

From 4d7afe82657e560a39a188d75684055736372d41 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:29:33 -0300
Subject: [PATCH 15/35] feat(uart): documents using the IDF default uart clock
 source

---
 cores/esp32/esp32-hal-uart.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h
index 0a84e39d64f..b3f853aa800 100644
--- a/cores/esp32/esp32-hal-uart.h
+++ b/cores/esp32/esp32-hal-uart.h
@@ -99,6 +99,7 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode);
 
 // Used to set the UART clock source mode. It must be set before calling uartBegin(), otherwise it won't have any effect.
 // Not all clock source are available to every SoC. The compatible option are listed here:
+// UART_SCLK_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
 // UART_SCLK_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
 // UART_SCLK_PLL_F80M     :: ESP32-C5, ESP32-C6, ESP32-C61 and ESP32-P4
 // UART_SCLK_PLL_F40M     :: ESP32-C2

From 673eff2c63a5bd62949a2a6aa9fb7a27918f278b Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:47:57 -0300
Subject: [PATCH 16/35] fix(uart): type missmatch may cause error

---
 cores/esp32/esp32-hal-uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 1df5804474b..8bb54c8f22f 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -997,7 +997,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   }
   bool retCode = true;
   soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
-  uint8_t previousClkSrc = uart->_uart_clock_source;
+  int8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
 #if !(CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE)

From 5ed541d4ddbd6ec50aaf7c89647f210baf16b495 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:48:22 -0300
Subject: [PATCH 17/35] fix(uart): type missmatch may cause error, test for -1

---
 cores/esp32/esp32-hal-uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 8bb54c8f22f..c7349b2d5b4 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -1045,7 +1045,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   }
   UART_MUTEX_LOCK();
   // if necessary, set the correct UART Clock Source before changing the baudrate
-  if (previousClkSrc != newClkSrc) {
+  if (previousClkSrc < 0 || previousClkSrc != newClkSrc) {
     HP_UART_SRC_CLK_ATOMIC() {
       uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
     }

From 530fcd0c373fad0190526059667ef4effe69fb8e Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 16:51:08 -0300
Subject: [PATCH 18/35] feat(uart): considering both HP and LP default uart
 clock source

---
 cores/esp32/HardwareSerial.cpp | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 26b6ffac813..b1aa3034b60 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -619,11 +619,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-  if (clkSrc == UART_CLK_SRC_DEFAULT) {
-    return uartSetClockSource(_uart, (uart_sclk_t) UART_SCLK_DEFAULT);
-  } else {
-    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
-  }
+    return uartSetClockSource(_uart, (int8_t) clkSrc); // allows negative values for UART_CLK_SRC_DEFAULT
 }
 
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.

From 7715d408aab1c87a50cae13514e38a60b7304f56 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 17:03:04 -0300
Subject: [PATCH 19/35] feat(uart): improve the defined value for
 UART_CLK_SRC_DEFAULT

---
 cores/esp32/HardwareSerial.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 22f9f6cd318..d3b27b44854 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -97,7 +97,7 @@ typedef enum {
 } hardwareSerial_error_t;
 
   typedef enum {
-    UART_CLK_SRC_DEFAULT = -1,
+    UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
 #if SOC_UART_SUPPORT_APB_CLK
     UART_CLK_SRC_APB = SOC_MOD_CLK_APB,
 #endif

From 4c6d92cfcc745e2a41a5021dcf6ea69ee3c694ba Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 17:05:08 -0300
Subject: [PATCH 20/35] fix(uart): using uart_sclk_t as hal level parameter

---
 cores/esp32/HardwareSerial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index b1aa3034b60..4a80f198cea 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -619,7 +619,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-    return uartSetClockSource(_uart, (int8_t) clkSrc); // allows negative values for UART_CLK_SRC_DEFAULT
+    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc); // allows negative values for UART_CLK_SRC_DEFAULT
 }
 
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.

From 291358d2a0b23a25b31c924a89689645005be235 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 17:11:53 -0300
Subject: [PATCH 21/35] feat(uart): apply default LP uart clock source

---
 cores/esp32/esp32-hal-uart.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index c7349b2d5b4..74c3ae72a93 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -1158,13 +1158,14 @@ bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
   if (uart->num >= SOC_UART_HP_NUM) {
     switch (clkSrc) {
       case UART_SCLK_XTAL:
-        uart->_uart_clock_source = SOC_MOD_CLK_XTAL_D2;
+        uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2;
         break;
       case UART_SCLK_RTC:
-        uart->_uart_clock_source = SOC_MOD_CLK_RTC_FAST;
+        uart->_uart_clock_source = LP_UART_SCLK_LP_FAST;
         break;
+      case UART_SCLK_DEFAULT:
       default:
-        uart->_uart_clock_source = -1;
+        uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
     }
   } else
 #endif

From 3e549d630bfd76963ce8c3bd2196ad1f8acc95d4 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 17:19:48 -0300
Subject: [PATCH 22/35] fix(uart): considers that it may set the LP UART as
 well

---
 cores/esp32/esp32-hal-uart.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 74c3ae72a93..6eb18098306 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -736,7 +736,14 @@ uart_t *uartBegin(
     uart->_tx_buffer_size = tx_buffer_size;
     uart->has_peek = false;
     uart->peek_byte = 0;
-    uart->_uart_clock_source = uart_config.source_clk;
+#if SOC_UART_LP_NUM >= 1
+    if (uart_nr >= SOC_UART_HP_NUM) {
+      uart->_uart_clock_source = uart_config.lp_source_clk;
+    } else
+#endif
+    {
+      uart->_uart_clock_source = uart_config.source_clk;
+    }
   }
   UART_MUTEX_UNLOCK();
 

From 0651cd5649067ce81236bc54f5a51a392f3b7e4c Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 20:13:55 -0300
Subject: [PATCH 23/35] feat(uart): using UART SCLK enum for uart clock source
 values

---
 cores/esp32/HardwareSerial.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index d3b27b44854..ee650da66fc 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -99,25 +99,25 @@ typedef enum {
   typedef enum {
     UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
 #if SOC_UART_SUPPORT_APB_CLK
-    UART_CLK_SRC_APB = SOC_MOD_CLK_APB,
+    UART_CLK_SRC_APB = UART_SCLK_APB,
 #endif
 #if SOC_UART_SUPPORT_PLL_F40M_CLK
-    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F40M,
+    UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
 #endif
 #if SOC_UART_SUPPORT_PLL_F80M_CLK
-    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F80M,
+    UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
 #endif
 #if CONFIG_IDF_TARGET_ESP32H2
-    UART_CLK_SRC_PLL = SOC_MOD_CLK_PLL_F48M,
+    UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
 #endif
 #if SOC_UART_SUPPORT_XTAL_CLK
-    UART_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
+    UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
 #endif
 #if SOC_UART_SUPPORT_RTC_CLK
-    UART_CLK_SRC_RTC_FAST = SOC_MOD_CLK_RC_FAST,
+    UART_CLK_SRC_RTC = UART_SCLK_RTC,
 #endif
 #if SOC_UART_SUPPORT_REF_TICK
-    UART_CLK_SRC_REF_TICK = SOC_MOD_CLK_REF_TICK,
+    UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
 #endif
 } SerialClkSrc;
 

From 145b0a11051d4ac5401576f67b924e61609a661b Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 20:17:06 -0300
Subject: [PATCH 24/35] fix(uart): using UART_CLK_SRC_RTC now

---
 cores/esp32/HardwareSerial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 4a80f198cea..d15586f3ad2 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -614,7 +614,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
 // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
 // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
-// UART_CLK_SRC_RTC_FAST     :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_CLK_SRC_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
 // UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source

From 5857606d0bc4d1b760ca06e473568532fca788dd Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Wed, 2 Apr 2025 20:19:10 -0300
Subject: [PATCH 25/35] fix(uart): documentation using UART_CLK_SRC_RTC now

---
 cores/esp32/HardwareSerial.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index ee650da66fc..63b285a4e0c 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -375,7 +375,7 @@ class HardwareSerial : public Stream {
   // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
   // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
   // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
-  // UART_CLK_SRC_RTC_FAST     :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+  // UART_CLK_SRC_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
   // UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
   // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
   // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source

From 4a931118b7518100e6913e65174880682a1111d2 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Thu, 3 Apr 2025 10:58:10 -0300
Subject: [PATCH 26/35] fix(uart): fix old commentary that is not correct
 anymore

---
 cores/esp32/HardwareSerial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index d15586f3ad2..7ad36e8cce9 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -619,7 +619,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc); // allows negative values for UART_CLK_SRC_DEFAULT
+    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
 }
 
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.

From 25b0326cfb420e193cdf576729bbdd81392e945f Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Thu, 3 Apr 2025 11:07:47 -0300
Subject: [PATCH 27/35] fix(uart): wrong identation in code line

---
 cores/esp32/HardwareSerial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 7ad36e8cce9..192b2796652 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -619,7 +619,7 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-    return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
+  return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
 }
 
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.

From 05337af5ab65a81d5ba07f1de33e759ac3ae056d Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Thu, 3 Apr 2025 12:06:03 -0300
Subject: [PATCH 28/35] fix(uart): using uart number as argument instead

---
 cores/esp32/HardwareSerial.cpp | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 192b2796652..9d0ed97be1f 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -619,9 +619,12 @@ bool HardwareSerial::setMode(SerialMode mode) {
 // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
 bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
-  return uartSetClockSource(_uart, (uart_sclk_t) clkSrc);
+  if (_uart) {
+    log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr);
+    return false;
+  }
+  return uartSetClockSource(_uart_nr, (uart_sclk_t) clkSrc);
 }
-
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
 // LP UART has FIFO of 16 bytes
 size_t HardwareSerial::setRxBufferSize(size_t new_size) {

From aa7a37f911c734d9b4d88fa5d53d080182ce8c63 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Thu, 3 Apr 2025 12:08:10 -0300
Subject: [PATCH 29/35] fix(uart): using uart number as argument in
 setClockSource()

---
 cores/esp32/esp32-hal-uart.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h
index b3f853aa800..41b005aa151 100644
--- a/cores/esp32/esp32-hal-uart.h
+++ b/cores/esp32/esp32-hal-uart.h
@@ -108,7 +108,7 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode);
 // UART_SCLK_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
 // UART_SCLK_REF_TICK     :: ESP32 and ESP32-S2
 // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only LP_UART_SCLK_LP_FAST (RTC_FAST) or LP_UART_SCLK_XTAL_D2 (XTAL/2) as Clock Source
-bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc);
+bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc);
 
 void uartStartDetectBaudrate(uart_t *uart);
 unsigned long uartDetectBaudrate(uart_t *uart);

From 57410d87fe3f1eb837445f87225065fe0f19b9b0 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Thu, 3 Apr 2025 12:11:54 -0300
Subject: [PATCH 30/35] fix(uart): using uart number as parameter in
 uartSetClockSource()

---
 cores/esp32/esp32-hal-uart.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 6eb18098306..95f9ad7ec45 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -1153,14 +1153,12 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode) {
 
 // this function will set the uart clock source 
 // it must be called before uartBegin(), otherwise it won't change any thing.
-bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
-  if (uart == NULL) {
-    return false;
-  }
-  if (uart_is_driver_installed(uart->num)) {
-    log_e("No Clock Source change was done. This function must be called before beginning UART%d.", uart->num);
+bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
+  if (uartNum >= SOC_UART_NUM) {
+    log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1);
     return false;
   }
+  uart_t *uart = &_uart_bus_array[uartNum];
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) {
     switch (clkSrc) {
@@ -1179,6 +1177,7 @@ bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
   {
     uart->_uart_clock_source = clkSrc;
   }
+  //log_i("UART%d set clock source to %d", uart->num, uart->_uart_clock_source);
   return true;
 }
 

From 9e1ae8ea4568d48daa6921d8d8acec4c05149bc7 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Fri, 4 Apr 2025 12:12:04 -0300
Subject: [PATCH 31/35] feat(uart): update Kconfig.projbuild to reflect
 functionality

---
 Kconfig.projbuild | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Kconfig.projbuild b/Kconfig.projbuild
index 120dbf8a701..7149698e6a2 100644
--- a/Kconfig.projbuild
+++ b/Kconfig.projbuild
@@ -125,9 +125,10 @@ config ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
         Overrides Arduino's automatic UART clock selection with the default clock from IDF (clk_tree_defs.h).
         By default, Arduino optimizes the UART clock automatically: XTAL clock for C2, S3, C3, C6, H2, P4 and 
         REF_TICK (<250k baud) or APB (>250k baud) for ESP32, S2.
+        It also overrrides HardwareSerial::setClockSource(), by always forcing the default uart clock source as defined in IDF. 
         Enable this option only if you need to force IDF's default clock instead of Arduino's optimized settings.
         It is generally recommended to leave this disabled unless specifically required.
-        Note: This configuration is not applicable to the low-power (LP) UART controller.
+        Note: This configuration is also applicable to the low-power (LP) UART controller, whenever this is available.
 
 choice ARDUINO_UDP_RUNNING_CORE
     bool "Core on which Arduino's UDP is running"

From 4279699c8d211bee037342e04bf3866cca4d05c4 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Fri, 4 Apr 2025 13:41:45 -0300
Subject: [PATCH 32/35] feat(uart): removing Kconfig.projbuild option to force
 default clk src

---
 Kconfig.projbuild | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/Kconfig.projbuild b/Kconfig.projbuild
index 7149698e6a2..9966463f8c1 100644
--- a/Kconfig.projbuild
+++ b/Kconfig.projbuild
@@ -118,18 +118,6 @@ config ARDUINO_SERIAL_EVENT_TASK_PRIORITY
     help
         Select at what priority you want the Serial Event task to run.
 
-config ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
-    bool "Force IDF default UART clock source"
-    default "n"
-    help
-        Overrides Arduino's automatic UART clock selection with the default clock from IDF (clk_tree_defs.h).
-        By default, Arduino optimizes the UART clock automatically: XTAL clock for C2, S3, C3, C6, H2, P4 and 
-        REF_TICK (<250k baud) or APB (>250k baud) for ESP32, S2.
-        It also overrrides HardwareSerial::setClockSource(), by always forcing the default uart clock source as defined in IDF. 
-        Enable this option only if you need to force IDF's default clock instead of Arduino's optimized settings.
-        It is generally recommended to leave this disabled unless specifically required.
-        Note: This configuration is also applicable to the low-power (LP) UART controller, whenever this is available.
-
 choice ARDUINO_UDP_RUNNING_CORE
     bool "Core on which Arduino's UDP is running"
     default ARDUINO_UDP_RUN_CORE0

From 589fa60cff82a3c82e2b25c470622abae8fa0958 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Fri, 4 Apr 2025 13:47:18 -0300
Subject: [PATCH 33/35] feat(uart): removes kconfig option to force uart
 default clk src

---
 cores/esp32/esp32-hal-uart.c | 22 ++--------------------
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 95f9ad7ec45..e80654ca2c6 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -666,24 +666,16 @@ uart_t *uartBegin(
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
   if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
-#if !(CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE)
     if (uart->_uart_clock_source > 0) {
       uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
-    } else 
-#endif
-    {
+    } else {
       uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
   } else
 #endif // SOC_UART_LP_NUM >= 1
   {
-#if CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
-    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
-    uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
-    log_v("Setting UART%d to use DEFAULT clock", uart_nr);
-#else
     if (uart->_uart_clock_source >= 0) {
       uart_config.source_clk = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
@@ -707,7 +699,6 @@ uart_t *uartBegin(
       log_v("Setting UART%d to use DEFAULT clock", uart_nr);
 #endif // SOC_UART_SUPPORT_XTAL_CLK
     }
-#endif // CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
   }
 
   UART_MUTEX_LOCK();
@@ -1007,24 +998,16 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   int8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
-#if !(CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE)
     if (uart->_uart_clock_source > 0) {
       newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
-    } else
-#endif
-    {
+    } else {
       newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart->num);
     }
   } else 
 #endif // SOC_UART_LP_NUM >= 1
   {
-#if CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
-    // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
-    // newClkSrc already set in the variable declaration
-    log_v("Setting UART%d to use DEFAULT clock", uart->num);
-#else
     if (uart->_uart_clock_source >= 0) {
       newClkSrc = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
@@ -1048,7 +1031,6 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
       log_v("Setting UART%d to use DEFAULT clock", uart->num);
 #endif // SOC_UART_SUPPORT_XTAL_CLK
     }
-#endif // CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE
   }
   UART_MUTEX_LOCK();
   // if necessary, set the correct UART Clock Source before changing the baudrate

From 84da5d8950dca39907f251db16f854acafbbdc25 Mon Sep 17 00:00:00 2001
From: Sugar Glider <rodrigo.garcia@espressif.com>
Date: Sun, 6 Apr 2025 12:20:29 -0300
Subject: [PATCH 34/35] fix(uart): replacing #if #endif by #if #elif #endif for
 the same enum

---
 cores/esp32/HardwareSerial.h | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 63b285a4e0c..420d83f7ea8 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -103,11 +103,9 @@ typedef enum {
 #endif
 #if SOC_UART_SUPPORT_PLL_F40M_CLK
     UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
-#endif
-#if SOC_UART_SUPPORT_PLL_F80M_CLK
+#elif SOC_UART_SUPPORT_PLL_F80M_CLK
     UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
-#endif
-#if CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32H2
     UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
 #endif
 #if SOC_UART_SUPPORT_XTAL_CLK

From 3e78c460ee86b7762bad0e6fcd33e6c37dcf5df4 Mon Sep 17 00:00:00 2001
From: "pre-commit-ci-lite[bot]"
 <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
Date: Sun, 6 Apr 2025 20:55:27 +0000
Subject: [PATCH 35/35] ci(pre-commit): Apply automatic fixes

---
 cores/esp32/HardwareSerial.cpp |  2 +-
 cores/esp32/HardwareSerial.h   | 19 +++++++-------
 cores/esp32/esp32-hal-uart.c   | 47 +++++++++++++++-------------------
 3 files changed, 32 insertions(+), 36 deletions(-)

diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index 9d0ed97be1f..6d762da21fb 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -623,7 +623,7 @@ bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
     log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr);
     return false;
   }
-  return uartSetClockSource(_uart_nr, (uart_sclk_t) clkSrc);
+  return uartSetClockSource(_uart_nr, (uart_sclk_t)clkSrc);
 }
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
 // LP UART has FIFO of 16 bytes
diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index 420d83f7ea8..e974f112701 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -96,26 +96,26 @@ typedef enum {
   UART_PARITY_ERROR
 } hardwareSerial_error_t;
 
-  typedef enum {
-    UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
+typedef enum {
+  UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
 #if SOC_UART_SUPPORT_APB_CLK
-    UART_CLK_SRC_APB = UART_SCLK_APB,
+  UART_CLK_SRC_APB = UART_SCLK_APB,
 #endif
 #if SOC_UART_SUPPORT_PLL_F40M_CLK
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
 #elif SOC_UART_SUPPORT_PLL_F80M_CLK
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
 #elif CONFIG_IDF_TARGET_ESP32H2
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
 #endif
 #if SOC_UART_SUPPORT_XTAL_CLK
-    UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
+  UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
 #endif
 #if SOC_UART_SUPPORT_RTC_CLK
-    UART_CLK_SRC_RTC = UART_SCLK_RTC,
+  UART_CLK_SRC_RTC = UART_SCLK_RTC,
 #endif
 #if SOC_UART_SUPPORT_REF_TICK
-    UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
+  UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
 #endif
 } SerialClkSrc;
 
@@ -380,6 +380,7 @@ class HardwareSerial : public Stream {
   bool setClockSource(SerialClkSrc clkSrc);
   size_t setRxBufferSize(size_t new_size);
   size_t setTxBufferSize(size_t new_size);
+
 protected:
   uint8_t _uart_nr;
   uart_t *_uart;
diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index e80654ca2c6..d2e98a2341a 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -665,23 +665,23 @@ uart_t *uartBegin(
   rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh;  // makes sure that it will be set correctly in the struct
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
-  if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+  if (uart_nr >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
-      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
     } else {
       uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
   } else
-#endif // SOC_UART_LP_NUM >= 1
+#endif  // SOC_UART_LP_NUM >= 1
   {
     if (uart->_uart_clock_source >= 0) {
-      uart_config.source_clk = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      uart_config.source_clk = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
-    } else {    
-    // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
-    // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+    } else {
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
       uart_config.source_clk = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
       log_v("Setting UART%d to use XTAL clock", uart_nr);
@@ -697,7 +697,7 @@ uart_t *uartBegin(
       // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
       uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
       log_v("Setting UART%d to use DEFAULT clock", uart_nr);
-#endif // SOC_UART_SUPPORT_XTAL_CLK
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
   }
 
@@ -997,23 +997,23 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
   int8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
-  if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+  if (uart->num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
-      newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      newClkSrc = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
     } else {
       newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart->num);
     }
-  } else 
-#endif // SOC_UART_LP_NUM >= 1
+  } else
+#endif  // SOC_UART_LP_NUM >= 1
   {
     if (uart->_uart_clock_source >= 0) {
-      newClkSrc = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      newClkSrc = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
-    } else {    
-    // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
-    // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+    } else {
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
       newClkSrc = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
       log_v("Setting UART%d to use XTAL clock", uart->num);
@@ -1029,7 +1029,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
       // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
       // using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration
       log_v("Setting UART%d to use DEFAULT clock", uart->num);
-#endif // SOC_UART_SUPPORT_XTAL_CLK
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
   }
   UART_MUTEX_LOCK();
@@ -1133,7 +1133,7 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode) {
   return retCode;
 }
 
-// this function will set the uart clock source 
+// this function will set the uart clock source
 // it must be called before uartBegin(), otherwise it won't change any thing.
 bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
   if (uartNum >= SOC_UART_NUM) {
@@ -1144,15 +1144,10 @@ bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) {
     switch (clkSrc) {
-      case UART_SCLK_XTAL:
-        uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2;
-        break;
-      case UART_SCLK_RTC:
-        uart->_uart_clock_source = LP_UART_SCLK_LP_FAST;
-        break;
+      case UART_SCLK_XTAL:    uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2; break;
+      case UART_SCLK_RTC:     uart->_uart_clock_source = LP_UART_SCLK_LP_FAST; break;
       case UART_SCLK_DEFAULT:
-      default:
-        uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
+      default:                uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
     }
   } else
 #endif