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* ----------------------------------------------------------------------
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* | Level | Last Value Used | Holes |
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* ----------------------------------------------------------------------
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- * | Module Init and Probe | 0x015b | 0x4b,0xba,0xfa |
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- * | | | 0x0x015a |
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- * | Mailbox commands | 0x1187 | 0x111a-0x111b |
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- * | | | 0x1155-0x1158 |
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- * | | | 0x1018-0x1019 |
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+ * | Module Init and Probe | 0x017d | 0x004b,0x0141 |
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+ * | | | 0x0144,0x0146 |
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+ * | | | 0x015b-0x0160 |
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+ * | | | 0x016e-0x0170 |
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+ * | Mailbox commands | 0x1187 | 0x1018-0x1019 |
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+ * | | | 0x10ca |
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* | | | 0x1115-0x1116 |
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- * | | | 0x10ca |
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+ * | | | 0x111a-0x111b |
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+ * | | | 0x1155-0x1158 |
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* | Device Discovery | 0x2095 | 0x2020-0x2022, |
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* | | | 0x2011-0x2012, |
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* | | | 0x2016 |
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* | | | 0x5084,0x5075 |
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* | | | 0x503d,0x5044 |
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* | Timer Routines | 0x6012 | |
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- * | User Space Interactions | 0x70e1 | 0x7018,0x702e, |
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- * | | | 0x7020,0x7024, |
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- * | | | 0x7039,0x7045, |
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- * | | | 0x7073-0x7075, |
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- * | | | 0x707b,0x708c, |
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- * | | | 0x70a5,0x70a6, |
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- * | | | 0x70a8,0x70ab, |
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- * | | | 0x70ad-0x70ae, |
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- * | | | 0x70d1-0x70db, |
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- * | | | 0x7047,0x703b |
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- * | | | 0x70de-0x70df, |
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+ * | User Space Interactions | 0x70e2 | 0x7018,0x702e |
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+ * | | | 0x7020,0x7024 |
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+ * | | | 0x7039,0x7045 |
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+ * | | | 0x7073-0x7075 |
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+ * | | | 0x70a5-0x70a6 |
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+ * | | | 0x70a8,0x70ab |
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+ * | | | 0x70ad-0x70ae |
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+ * | | | 0x70d7-0x70db |
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+ * | | | 0x70de-0x70df |
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* | Task Management | 0x803d | 0x8025-0x8026 |
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* | | | 0x800b,0x8039 |
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* | AER/EEH | 0x9011 | |
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* | | | 0xb13c-0xb140 |
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* | | | 0xb149 |
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* | MultiQ | 0xc00c | |
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- * | Misc | 0xd010 | |
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+ * | Misc | 0xd2ff | 0xd017-0xd019 |
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+ * | | | 0xd020 |
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+ * | | | 0xd02e-0xd0ff |
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+ * | | | 0xd101-0xd1fe |
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+ * | | | 0xd212-0xd2fe |
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* | Target Mode | 0xe070 | 0xe021 |
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* | Target Mode Management | 0xf072 | 0xf002-0xf003 |
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* | | | 0xf046-0xf049 |
@@ -104,7 +108,87 @@ qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
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return ptr + (rsp -> length * sizeof (response_t ));
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}
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- static int
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+ int
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+ qla27xx_dump_mpi_ram (struct qla_hw_data * ha , uint32_t addr , uint32_t * ram ,
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+ uint32_t ram_dwords , void * * nxt )
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+ {
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+ int rval ;
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+ uint32_t cnt , stat , timer , dwords , idx ;
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+ uint16_t mb0 , mb1 ;
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+ struct device_reg_24xx __iomem * reg = & ha -> iobase -> isp24 ;
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+ dma_addr_t dump_dma = ha -> gid_list_dma ;
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+ uint32_t * dump = (uint32_t * )ha -> gid_list ;
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+
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+ rval = QLA_SUCCESS ;
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+ mb0 = 0 ;
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+
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+ WRT_REG_WORD (& reg -> mailbox0 , MBC_LOAD_DUMP_MPI_RAM );
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+ clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags );
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+
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+ dwords = qla2x00_gid_list_size (ha ) / 4 ;
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+ for (cnt = 0 ; cnt < ram_dwords && rval == QLA_SUCCESS ;
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+ cnt += dwords , addr += dwords ) {
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+ if (cnt + dwords > ram_dwords )
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+ dwords = ram_dwords - cnt ;
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+
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+ WRT_REG_WORD (& reg -> mailbox1 , LSW (addr ));
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+ WRT_REG_WORD (& reg -> mailbox8 , MSW (addr ));
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+
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+ WRT_REG_WORD (& reg -> mailbox2 , MSW (dump_dma ));
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+ WRT_REG_WORD (& reg -> mailbox3 , LSW (dump_dma ));
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+ WRT_REG_WORD (& reg -> mailbox6 , MSW (MSD (dump_dma )));
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+ WRT_REG_WORD (& reg -> mailbox7 , LSW (MSD (dump_dma )));
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+
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+ WRT_REG_WORD (& reg -> mailbox4 , MSW (dwords ));
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+ WRT_REG_WORD (& reg -> mailbox5 , LSW (dwords ));
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+
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+ WRT_REG_WORD (& reg -> mailbox9 , 0 );
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+ WRT_REG_DWORD (& reg -> hccr , HCCRX_SET_HOST_INT );
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+
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+ ha -> flags .mbox_int = 0 ;
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+ for (timer = 6000000 ; timer ; timer -- ) {
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+ /* Check for pending interrupts. */
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+ stat = RD_REG_DWORD (& reg -> host_status );
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+ if (stat & HSRX_RISC_INT ) {
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+ stat &= 0xff ;
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+
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+ if (stat == 0x1 || stat == 0x2 ||
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+ stat == 0x10 || stat == 0x11 ) {
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+ set_bit (MBX_INTERRUPT ,
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+ & ha -> mbx_cmd_flags );
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+
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+ mb0 = RD_REG_WORD (& reg -> mailbox0 );
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+ mb1 = RD_REG_WORD (& reg -> mailbox1 );
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+
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+ WRT_REG_DWORD (& reg -> hccr ,
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+ HCCRX_CLR_RISC_INT );
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+ RD_REG_DWORD (& reg -> hccr );
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+ break ;
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+ }
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+
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+ /* Clear this intr; it wasn't a mailbox intr */
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+ WRT_REG_DWORD (& reg -> hccr , HCCRX_CLR_RISC_INT );
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+ RD_REG_DWORD (& reg -> hccr );
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+ }
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+ udelay (5 );
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+ }
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+ ha -> flags .mbox_int = 1 ;
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+
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+ if (test_and_clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags )) {
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+ rval = mb0 & MBS_MASK ;
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+ for (idx = 0 ; idx < dwords ; idx ++ )
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+ ram [cnt + idx ] = IS_QLA27XX (ha ) ?
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+ le32_to_cpu (dump [idx ]) : swab32 (dump [idx ]);
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+ } else {
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+ rval = QLA_FUNCTION_FAILED ;
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+ }
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+ }
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+
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+ * nxt = rval == QLA_SUCCESS ? & ram [cnt ] : NULL ;
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+ return rval ;
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+ }
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+
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+ int
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qla24xx_dump_ram (struct qla_hw_data * ha , uint32_t addr , uint32_t * ram ,
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uint32_t ram_dwords , void * * nxt )
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{
@@ -139,6 +223,7 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
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WRT_REG_WORD (& reg -> mailbox5 , LSW (dwords ));
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WRT_REG_DWORD (& reg -> hccr , HCCRX_SET_HOST_INT );
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+ ha -> flags .mbox_int = 0 ;
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for (timer = 6000000 ; timer ; timer -- ) {
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/* Check for pending interrupts. */
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stat = RD_REG_DWORD (& reg -> host_status );
@@ -164,11 +249,13 @@ qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
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}
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udelay (5 );
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}
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+ ha -> flags .mbox_int = 1 ;
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if (test_and_clear_bit (MBX_INTERRUPT , & ha -> mbx_cmd_flags )) {
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rval = mb0 & MBS_MASK ;
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for (idx = 0 ; idx < dwords ; idx ++ )
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- ram [cnt + idx ] = swab32 (dump [idx ]);
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+ ram [cnt + idx ] = IS_QLA27XX (ha ) ?
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+ le32_to_cpu (dump [idx ]) : swab32 (dump [idx ]);
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} else {
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rval = QLA_FUNCTION_FAILED ;
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}
@@ -208,7 +295,7 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
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return buf ;
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}
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- static inline int
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+ int
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qla24xx_pause_risc (struct device_reg_24xx __iomem * reg )
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{
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int rval = QLA_SUCCESS ;
@@ -227,7 +314,7 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
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return rval ;
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}
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- static int
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+ int
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qla24xx_soft_reset (struct qla_hw_data * ha )
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{
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int rval = QLA_SUCCESS ;
@@ -537,7 +624,7 @@ qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
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struct qla2xxx_mq_chain * mq = ptr ;
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device_reg_t __iomem * reg ;
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- if (!ha -> mqenable || IS_QLA83XX (ha ))
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+ if (!ha -> mqenable || IS_QLA83XX (ha ) || IS_QLA27XX ( ha ) )
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return ptr ;
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mq = ptr ;
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