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Haijun Liudavem330
Haijun Liu
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davem330
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net: wwan: t7xx: Add core components
Registers the t7xx device driver with the kernel. Setup all the core components: PCIe layer, Modem Host Cross Core Interface (MHCCIF), modem control operations, modem state machine, and build infrastructure. * PCIe layer code implements driver probe and removal. * MHCCIF provides interrupt channels to communicate events such as handshake, PM and port enumeration. * Modem control implements the entry point for modem init, reset and exit. * The modem status monitor is a state machine used by modem control to complete initialization and stop. It is used also to propagate exception events reported by other components. Signed-off-by: Haijun Liu <[email protected]> Signed-off-by: Chandrashekar Devegowda <[email protected]> Co-developed-by: Ricardo Martinez <[email protected]> Signed-off-by: Ricardo Martinez <[email protected]> Reviewed-by: Loic Poulain <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergey Ryazanov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent 39d4390 commit 13e920d

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‎drivers/net/wwan/Kconfig

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@@ -105,6 +105,20 @@ config IOSM
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If unsure, say N.
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config MTK_T7XX
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tristate "MediaTek PCIe 5G WWAN modem T7xx device"
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depends on PCI
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help
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Enables MediaTek PCIe based 5G WWAN modem (T7xx series) device.
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Adapts WWAN framework and provides network interface like wwan0
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and tty interfaces like wwan0at0 (AT protocol), wwan0mbim0
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(MBIM protocol), etc.
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To compile this driver as a module, choose M here: the module will be
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called mtk_t7xx.
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If unsure, say N.
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endif # WWAN
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endmenu

‎drivers/net/wwan/Makefile

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@@ -13,3 +13,4 @@ obj-$(CONFIG_MHI_WWAN_MBIM) += mhi_wwan_mbim.o
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obj-$(CONFIG_QCOM_BAM_DMUX) += qcom_bam_dmux.o
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obj-$(CONFIG_RPMSG_WWAN_CTRL) += rpmsg_wwan_ctrl.o
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obj-$(CONFIG_IOSM) += iosm/
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obj-$(CONFIG_MTK_T7XX) += t7xx/

‎drivers/net/wwan/t7xx/Makefile

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# SPDX-License-Identifier: GPL-2.0-only
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ccflags-y += -Werror
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obj-${CONFIG_MTK_T7XX} := mtk_t7xx.o
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mtk_t7xx-y:= t7xx_pci.o \
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t7xx_pcie_mac.o \
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t7xx_mhccif.o \
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t7xx_state_monitor.o \
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t7xx_modem_ops.o \
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t7xx_cldma.o \
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t7xx_hif_cldma.o \

‎drivers/net/wwan/t7xx/t7xx_mhccif.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <[email protected]>
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* Sreehari Kancharla <[email protected]>
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*
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* Contributors:
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* Amir Hanania <[email protected]>
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* Ricardo Martinez <[email protected]>
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*/
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#include <linux/bits.h>
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#include <linux/completion.h>
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#include <linux/dev_printk.h>
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#include <linux/io.h>
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#include <linux/irqreturn.h>
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#include "t7xx_mhccif.h"
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#include "t7xx_modem_ops.h"
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#include "t7xx_pci.h"
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#include "t7xx_pcie_mac.h"
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#include "t7xx_reg.h"
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static void t7xx_mhccif_clear_interrupts(struct t7xx_pci_dev *t7xx_dev, u32 mask)
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{
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void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
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/* Clear level 2 interrupt */
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iowrite32(mask, mhccif_pbase + REG_EP2RC_SW_INT_ACK);
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/* Ensure write is complete */
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t7xx_mhccif_read_sw_int_sts(t7xx_dev);
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/* Clear level 1 interrupt */
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t7xx_pcie_mac_clear_int_status(t7xx_dev, MHCCIF_INT);
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}
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static irqreturn_t t7xx_mhccif_isr_thread(int irq, void *data)
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{
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struct t7xx_pci_dev *t7xx_dev = data;
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u32 int_status, val;
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val = T7XX_L1_1_BIT(1) | T7XX_L1_2_BIT(1);
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iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR);
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int_status = t7xx_mhccif_read_sw_int_sts(t7xx_dev);
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if (int_status & D2H_SW_INT_MASK) {
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int ret = t7xx_pci_mhccif_isr(t7xx_dev);
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if (ret)
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dev_err(&t7xx_dev->pdev->dev, "PCI MHCCIF ISR failure: %d", ret);
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}
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t7xx_mhccif_clear_interrupts(t7xx_dev, int_status);
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t7xx_pcie_mac_set_int(t7xx_dev, MHCCIF_INT);
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return IRQ_HANDLED;
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}
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u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev)
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{
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return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_STS);
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}
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void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val)
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{
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iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_SET);
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}
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void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val)
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{
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iowrite32(val, t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK_CLR);
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}
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u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev)
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{
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return ioread32(t7xx_dev->base_addr.mhccif_rc_base + REG_EP2RC_SW_INT_EAP_MASK);
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}
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static irqreturn_t t7xx_mhccif_isr_handler(int irq, void *data)
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{
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return IRQ_WAKE_THREAD;
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}
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void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev)
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{
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t7xx_dev->base_addr.mhccif_rc_base = t7xx_dev->base_addr.pcie_ext_reg_base +
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MHCCIF_RC_DEV_BASE -
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t7xx_dev->base_addr.pcie_dev_reg_trsl_addr;
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t7xx_dev->intr_handler[MHCCIF_INT] = t7xx_mhccif_isr_handler;
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t7xx_dev->intr_thread[MHCCIF_INT] = t7xx_mhccif_isr_thread;
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t7xx_dev->callback_param[MHCCIF_INT] = t7xx_dev;
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}
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void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel)
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{
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void __iomem *mhccif_pbase = t7xx_dev->base_addr.mhccif_rc_base;
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iowrite32(BIT(channel), mhccif_pbase + REG_RC2EP_SW_BSY);
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iowrite32(channel, mhccif_pbase + REG_RC2EP_SW_TCHNUM);
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}

‎drivers/net/wwan/t7xx/t7xx_mhccif.h

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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <[email protected]>
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* Sreehari Kancharla <[email protected]>
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*
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* Contributors:
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* Amir Hanania <[email protected]>
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* Ricardo Martinez <[email protected]>
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*/
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#ifndef __T7XX_MHCCIF_H__
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#define __T7XX_MHCCIF_H__
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#include <linux/types.h>
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#include "t7xx_pci.h"
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#include "t7xx_reg.h"
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#define D2H_SW_INT_MASK (D2H_INT_EXCEPTION_INIT | \
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D2H_INT_EXCEPTION_INIT_DONE | \
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D2H_INT_EXCEPTION_CLEARQ_DONE | \
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D2H_INT_EXCEPTION_ALLQ_RESET | \
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D2H_INT_PORT_ENUM | \
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D2H_INT_ASYNC_MD_HK)
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void t7xx_mhccif_mask_set(struct t7xx_pci_dev *t7xx_dev, u32 val);
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void t7xx_mhccif_mask_clr(struct t7xx_pci_dev *t7xx_dev, u32 val);
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u32 t7xx_mhccif_mask_get(struct t7xx_pci_dev *t7xx_dev);
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void t7xx_mhccif_init(struct t7xx_pci_dev *t7xx_dev);
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u32 t7xx_mhccif_read_sw_int_sts(struct t7xx_pci_dev *t7xx_dev);
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void t7xx_mhccif_h2d_swint_trigger(struct t7xx_pci_dev *t7xx_dev, u32 channel);
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#endif /*__T7XX_MHCCIF_H__ */

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