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Commit 7b66c6e

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Dylan McKay
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[AVR] Add 16-bit STS instruction
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lib/Target/AVR/AVRInstrInfo.td

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@@ -87,6 +87,7 @@ def imm0_63_neg : PatLeaf<(imm),
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}], imm16_neg_XFORM>;
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def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
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def uimm7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
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def ioaddr_XFORM : SDNodeXForm<imm,
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[{
@@ -1275,6 +1276,16 @@ def STSKRr : F32DM<0b1,
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[(store i8:$rd, imm:$k)]>,
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Requires<[HasSRAM]>;
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// Indirect store from register to data space.
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// FIXME:
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// - make this a physical instruction (not a pseudi)
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// - map r0..r15 onto r16..r31 so that the numbers match up.
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def STS16KRr : Pseudo<(outs),
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(ins uimm7:$k, GPR8hi:$rd),
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"sts\t$k, $rd",
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[store i8:$rd, imm:$k]>,
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Requires<[HasTinyEncoding]>;
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// STSW K+1:K, Rr+1:Rr
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//
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// Expands to:

lib/Target/AVR/AVRRegisterInfo.td

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@@ -130,6 +130,13 @@ def GPR8lo : RegisterClass<"AVR", [i8], 8,
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add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
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)>;
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// Upper registers r0..r15
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def GPR8hi : RegisterClass<"AVR", [i8], 8,
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(
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add R16, R17, R18, R19, R20, R21, R22, R23,
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R24, R25, R26, R27, R28, R29, R30, R31
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)>;
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// 8-bit register class for instructions which take immediates.
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def LD8 : RegisterClass<"AVR", [i8], 8,
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(

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