[AVR] Fix atomic stores bug

In ISel, we allowed any register of [X,Y,Z]. We expanded to an
instruction which required one of [Y, Z]. This would sometimes fail if X
was allocated and used in the sequence.

Author: Dylan McKay

lib/Target/AVR/AVRInstrInfo.td

@@ -1242,7 +1242,7 @@ class AtomicLoad<PatFrag Op, RegisterClass DRC> :
          [(set DRC:$rd, (Op i16:$rr))]>;
 
 class AtomicStore<PatFrag Op, RegisterClass DRC> :
-  Pseudo<(outs), (ins LDSTPtrReg:$rd, DRC:$rr), "atomic_op",
+  Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
          [(Op i16:$rd, DRC:$rr)]>;
 
 class AtomicLoadOp<PatFrag Op, RegisterClass DRC> :

test/CodeGen/AVR/atomics/store16.ll

@@ -11,3 +11,15 @@ define void @atomic_store16(i16* %foo) {
   ret void
 }
 
+; CHECK-LABEL: monotonic
+; CHECK:      in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: st Z, r24
+; CHECK-NEXT: std Z+1, r25
+; CHECK-NEXT: out 63, r0
+define void @monotonic(i16) {
+entry-block:
+  store atomic i16 %0, i16* undef monotonic, align 2
+  ret void
+}
+